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1.5MHz, 600mA Synchronous Step-Down Regulator in ThinSOT
FEATURES DESCRIPTIO
�? High Efficiency: Up to 96%
�? Very Low Quiescent Current: Only 20µA During Operation
�? 600mA Output Current
�? 2.5V to 5.5V Input Voltage Range
�? 1.5MHz Constant Frequency Operation
�? No Schottky Diode Required
�? Low Dropout Operation: 100% Duty Cycle
�? 0.6V Reference Allows Low Output Voltages
�? Shutdown Mode Draws �?1µA Supply Current
�? Current Mode Operation for Excellent Line and
Load Transient Response
�? Overtemperature Protected
�? Low Profile (1mm) ThinSOTTM Package
APPLICATIO S
�? Cellular Telephones
�? Personal Information Appliances
�? Wireless and DSL Modems
�? Digital Still Cameras
�? MP3 Players
�? Portable Instruments
The LTC®3406 is a high efficiency monolithic synchro- nous buck regulator using a constant frequency, current mode architecture. The device is available in an adjustable version and fixed output voltages of 1.5V and 1.8V. Supply current during operation is only 20µA and drops to �?1µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3406 ideally suited for single Li-Ion battery-pow- ered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Automatic Burst Mode® operation increases efficiency at light loads, further extending battery life.
Switching frequency is internally set at 1.5MHz, allowing the use of small surface mount inductors and capacitors.
The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.6V feed- back reference voltage. The LTC3406 is available in a low profile (1mm) ThinSOT package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
Protected by U.S. Patents, including 6580258, 5481178.
TYPICAL APPLICATIO
VIN = 2.7V
TO 5.5V
2.2µH*
VIN = 3.6V
4.7µF CER
LTC3406-1.8
VIN = 4.2V
3406 F01a
*MURATA LQH32CN2R2M33
**TAIYO YUDEN JMK212BJ475MG
VOUT = 1.8V
10 100 1000
†TAIYO YUDEN JMK316BJ106ML
OUTPUT CURRENT (mA)
Figure 1a. High Efficiency Step-Down Converter
3406 F01b
Figure 1b. Efficiency vs Load Current
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply Voltage .................................. �?0.3V to 6V RUN, VFB Voltages ..................................... �?0.3V to VIN SW Voltage .................................. �?0.3V to (VIN + 0.3V) P-Channel Switch Source Current (DC) ............. 800mA N-Channel Switch Sink Current (DC) ................. 800mA
Peak SW Sink and Source Current ........................ 1.3A Operating Temperature Range (Note 2) .. �?40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................ �?65°C to 150°C Lead Temperature (Soldering, 10 sec) ................. 300°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
S5 PACKAGE
ORDER PART NUMBER
LTC3406ES5
S5 PART MARKING
TOP VIEW
S5 PACKAGE
ORDER PART NUMBER
LTC3406ES5-1.5
LTC3406ES5-1.8
S5 PART MARKING
5-LEAD PLASTIC TSOT-23
TJMAX = 125°C, JA = 250°C/ W, JC = 90°C/ W
5-LEAD PLASTIC TSOT-23
TJMAX = 125°C, JA = 250°C/ W, JC = 90°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The �?denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 3.6V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IVFB Feedback Current �? ±30 nA VFB Regulated Feedback Voltage LTC3406 (Note 4) TA = 25°C 0.5880 0.6 0.6120 V
LTC3406 (Note 4) 0°C TA �?85°C 0.5865 0.6 0.6135 V LTC3406 (Note 4) �?40°C �?TA �?85°C �?0.5850 0.6 0.6150 V
∆VFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 4) �? 0.04 0.4 %/V VOUT Regulated Output Voltage LTC3406-1.5, IOUT = 100mA �? 1.455 1.500 1.545 V
LTC3406-1.8, IOUT = 100mA �?1.746 1.800 1.854 V
∆VOUT Output Voltage Line Regulation VIN = 2.5V to 5.5V �? 0.04 0.4 %/V IPK Peak Inductor Current VIN = 3V, VFB = 0.5V or VOUT = 90%, 0.75 1 1.25 A
Duty Cycle < 35%
VLOADREG Output Voltage Load Regulation 0.5 % VIN Input Voltage Range �? 2.5 5.5 V IS Input DC Bias Current (Note 5)
Active Mode VFB = 0.5V or VOUT = 90%, ILOAD = 0A 300 400 µA
Sleep Mode VFB = 0.62V or VOUT = 103%, ILOAD = 0A 20 35 µA
Shutdown VRUN = 0V, VIN = 4.2V 0.1 1 µA
fOSC Oscillator Frequency VFB = 0.6V or VOUT = 100% �? 1.2 1.5 1.8 MHz
VFB = 0V or VOUT = 0V 210 kHz
RPFET RDS(ON) of P-Channel FET ISW = 100mA 0.4 0.5 �?RNFET RDS(ON) of N-Channel FET ISW = �?100mA 0.35 0.45 �?ILSW SW Leakage VRUN = 0V, VSW = 0V or 5V, VIN = 5V ± 0.01 ± 1 µA
ELECTRICAL CHARACTERISTICS
The �?denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 3.6V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VRUN RUN Threshold �? 0.3 1 1.5 V IRUN RUN Leakage Current �? ± 0.01 ± 1 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: The LTC3406E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the �?0°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula:
LTC3406: TJ = TA + (PD)(250°C/ W)
Note 4: The LTC3406 is tested in a proprietary test mode that connects
VFB to the output of the error amplifier.
Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency.
TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure1a Except for the Resistive Divider Resistor Values)
Efficiency vs Input Voltage Efficiency vs Output Current Efficiency vs Output Current
IOUT = 100mA IOUT = 10mA IOUT = 1mA
VOUT = 1.2V
VOUT = 1.5V
VIN = 2.7V
VIN = 4.2V
VOUT = 1.8V
IOUT = 600mA
IOUT = 0.1mA
VIN = 4.2V
VIN = 3.6V
VIN = 3.6V
2 3 4 5 6
10 100 1000
10 100 1000
INPUT VOLTAGE (V)
3406 G01
OUTPUT CURRENT (mA)
3406 G02
OUTPUT CURRENT (mA)
3406 G03
Efficiency vs Output Current
VOUT = 2.5V VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
Reference Voltage vs
Temperature
VIN = 3.6V
Oscillator Frequency vs
Temperature
VIN = 3.6V
10 100 1000
75 100 125
75 100 125
OUTPUT CURRENT (mA)
3406 G04
TEMPERATURE (°C)
3406 G05
TEMPERATURE (°C)
3406 G06
TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure1a Except for the Resistive Divider Resistor Values)
Oscillator Frequency vs
Supply Voltage Output Voltage vs Load Current RDS(ON) vs Input Voltage
VIN = 3.6V
MAIN SWITCH
SYNCHRONOUS SWITCH
3 4 5 6
100 200 300 400 500 600 700 800 900
0 1 2 3 4 5 6 7
SUPPLY VOLTAGE (V)
3406 G07
LOAD CURRENT (mA)
3406 G08
INPUT VOLTAGE (V)
3406 G09
RDS(ON) vs Temperature Supply Current vs Supply Voltage Supply Current vs Temperature
VIN = 2.7V
VOUT = 1.8V
VIN = 4.2V
VIN = 3.6V
ILOAD = 0A
VOUT = 1.8V
40 ILOAD = 0A
MAIN SWITCH 5 5
SYNCHRONOUS SWITCH
75 100 125
2 3 4 5 6
25 50 75
100 125
TEMPERATURE (°C)
3406 G10
SUPPLY VOLTAGE (V)
3406 G11
TEMPERATURE (°C)
3406 G12
Switch Leakage vs Temperature Switch Leakage vs Input Voltage Burst Mode Operation
VIN = 5.5V RUN = 0V
MAIN SWITCH SYNCHRONOUS SWITCH
RUN = 0V
SYNCHRONOUS SWITCH
MAIN SWITCH
100mV/DIV
AC COUPLED
200mA/DIV
VIN = 3.6V VOUT = 1.8V ILOAD = 50mA
4µs/DIV
3406 G15
75 100 125
0 1 2 3 4 5 6
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3406 G13
3406 G14
TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure 1a Except for the Resistive Divider Resistor Values)
Start-Up from Shutdown Load Step Load Step
500mA/DIV
100mV/DIV
AC COUPLED
500mA/DIV
500mA/DIV
100mV/DIV
AC COUPLED
500mA/DIV
500mA/DIV
VIN = 3.6V VOUT = 1.8V
40µs/DIV
3406 G16
VIN = 3.6V VOUT = 1.8V
20µs/DIV
3406 G17
VIN = 3.6V VOUT = 1.8V
20µs/DIV
3406 G18
ILOAD = 600mA
ILOAD = 0mA TO 600mA
ILOAD = 50mA TO 600mA
100mV/DIV
AC COUPLED
500mA/DIV
500mA/DIV
Load Step Load Step
100mV/DIV
AC COUPLED
500mA/DIV
500mA/DIV
VIN = 3.6V VOUT = 1.8V
20µs/DIV
3406 G19
VIN = 3.6V VOUT = 1.8V
20µs/DIV
3406 G20
ILOAD = 100mA TO 600mA
ILOAD = 200mA TO 600mA
PI FU CTIO S
RUN (Pin 1): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1µA supply current. Do not leave RUN floating.
GND (Pin 2): Ground Pin.
SW (Pin 3): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchro- nous power MOSFET switches.
VIN (Pin 4): Main Supply Pin. Must be closely decoupled to GND, Pin 2, with a 2.2µF or greater ceramic capacitor.
VFB (Pin 5) (LTC3406): Feedback Pin. Receives the feed- back voltage from an external resistive divider across the output.
VOUT (Pin 5) (LTC3406-1.5/LTC3406-1.8): Output Volt- age Feedback Pin. An internal resistive divider divides the output voltage down for comparison to the internal refer- ence voltage.
FU CTIO AL DIAGRA
SLOPE COMP
VFB/VOUT
LTC3406-1.5
R1 + R2 = 550k
LTC3406-1.8
FREQ SHIFT
R1 0.6V
4 VIN
R1 + R2 = 540k R2 S Q R Q
0.6V REF SHUTDOWN
RS LATCH SWITCHING LOGIC
AND BLANKING CIRCUIT
ANTI- SHOOT- THRU
3406 BD
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3406 uses a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current com- parator, ICOMP, resets the RS latch. The peak inductor
current at which ICOMP resets the RS latch, is controlled by
the output of error amplifier EA. When the load current
increases, it causes a slight decrease in the feedback voltage, FB, relative to the 0.6V reference, which in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new load cur- rent. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or
the beginning of the next clock cycle.
Burst Mode Operation
The LTC3406 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand.
In Burst Mode operation, the peak current of the inductor is set to approximately 200mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 20µA. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA amplifier’s output rises above the sleep threshold signal- ing the BURST comparator to trip and turn the top MOSFET on. This process repeats at a rate that is dependent on the load demand.
OPERATIO (Refer to Functional Diagram)
Short-Circuit Protection
When the output is shorted to ground, the frequency of the oscillator is reduced to about 210kHz, 1/7 the nominal frequency. This frequency foldback ensures that the in- ductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 1.5MHz when VFB or VOUT rises above 0V.
Dropout Operation
As the input supply voltage decreases to a value approach- ing the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor.
An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases
in the maximum output current as a function of input voltage for various output voltages.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3406 uses a patent-pending scheme that counteracts this compensat- ing ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles.
VOUT = 1.8V
(see Typical Performance Characteristics). Therefore, the
user should calculate the power dissipation when the LTC3406 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Informa- tion section).
VOUT = 1.5V
VOUT = 2.5V
Low Supply Operation
The LTC3406 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is
3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
5.0 5.5
3406 F02
reduced at this low voltage. Figure 2 shows the reduction
Figure 2. Maximum Output Current vs Input Voltage
APPLICATIO S I FOR ATIO
The basic LTC3406 application circuit is shown in Figure 1. External component selection is driven by the load require- ment and begins with the selection of L followed by CIN and COUT.
Inductor Selection
For most applications, the value of the inductor will fall in the range of 1µH to 4.7µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in equation 1. A reasonable starting point for setting ripple current is ∆IL = 240mA (40% of 600mA).
inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3406 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3406 applications.
Table 1. Representative Surface Mount Inductors
PART VALUE DCR MAX DC SIZE NUMBER (µH) (�?MAX) CURRENT (A) W × L × H (mm3)
Sumida 1.5 0.043 1.55 3.8 × 3.8 × 1.8
CDRH3D16 2.2 0.075 1.20
3.3 0.110 1.10
4.7 0.162 0.90
Sumida 2.2 0.116 0.950 3.5 × 4.3 × 0.8
CMD4D06 3.3 0.174 0.770
4.7 0.216 0.750
∆I = 1 V
�?�?VOUT �?L OUT �?�?Panasonic 3.3 0.17 1.00 4.5 × 5.4 × 1.2
�?VIN �?ELT5KT 4.7 0.20 0.95
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 720mA rated inductor should be enough for most applications (600mA
+ 120mA). For better efficiency, choose a low DC-resis-
tance inductor.
The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately
200mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase.
Inductor Core Selection
Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy mate- rials are small and don’t radiate much energy, but gener- ally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style
Murata 1.0 0.060 1.00 2.5 × 3.2 × 2.0
LQH32CN 2.2 0.097 0.79
4.7 0.150 0.65
CIN and COUT Selection
In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum
RMS capacitor current is given by:
C required I �?I [VOUT (VIN �?VOUT )]
IN RMS OMAX VIN
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufac- turer if there is any question.
APPLICATIO S I FOR ATIO
The selection of COUT is driven by the required effective series resistance (ESR).
Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆VOUT is deter- mined by:
induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part.
When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These
∆V �?∆I
�?ESR + 1 �?dielectrics have the best temperature and voltage charac-
OUT L �?8fCOUT �?teristics of all the ceramics for a given value and size.
where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ∆IL increases with input voltage.
Output Voltage Programming (LTC3406 Only)
In the adjustable version, the output voltage is set by a resistive divider according to the following formula:
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the case
�?1+ �?of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer
The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 3.
0.6V �?VOUT �?5.5V R2
for other specific recommendations.
Using Ceramic Input and Output Capacitors
LTC3406
3406 F03
Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3406’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size.
However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can
Figure 3. Setting the LTC3406 Output Voltage
Efficiency Considerations
The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as:
Efficiency = 100% �?(L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3406 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I2R
loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 4.
VOUT = 1.2V
VOUT = 1.5V
0.1 VOUT = 1.8V VOUT = 2.5V
0.00001
2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped�? between the main
switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 �?DC) The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current.
Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss.
Thermal Considerations
10 100 1000
LOAD CURRENT (mA)
3406 F04
In most applications the LTC3406 does not dissipate much heat due to its high efficiency. But, in applications
Figure 4. Power Lost vs Load Current
1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical character- istics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages.
where the LTC3406 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maxi- mum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance.
To avoid the LTC3406 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The tempera- ture rise is given by:
TR = (PD)(JA)
where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature.
APPLICATIO S I FOR ATIO
The junction temperature, TJ, is given by: TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3406 in dropout at an input voltage of 2.7V, a load current of 600mA and an ambient temperature of 70°C. From the typical perfor- mance graph of switch resistance, the RDS(ON) of the
P-channel switch at 70°C is approximately 0.52�? There-
fore, power dissipated by the part is:
A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 �?CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
PD = I 2 �?R
= 187.2mW
130mA.
For the SOT-23 package, the JA is 250°C/ W. Thus, the junction temperature of the regulator is:
TJ = 70°C + (0.1872)(250) = 116.8°C
which is below the maximum junction temperature of
Note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD �?ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, which generates a feedback error signal.
The regulator loop then acts to return VOUT to its steady-
state value. During this recovery time VOUT can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control loop theory, see Application Note 76.
PC Board Layout Checklist
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3406. These items are also illustrated graphically in Figures 5 and 6. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide.
2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be con- nected between the (+) plate of COUT and ground.
3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
VFB node.
5. Keep the (�? plates of CIN and COUT as close as possible.
APPLICATIO S I FOR ATIO
LTC3406
LTC3406-1.8
BOLD LINES INDICATE HIGH CURRENT PATHS
3406 F05a
3406 F05b
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 5a. LTC3406 Layout Diagram
Figure 5b. LTC3406-1.8 Layout Diagram
VIA TO GND
VIA TO VIN
LTC3406
VIA TO VOUT
VIA TO VOUT
VIA TO VIN
LTC3406-1.8
COUT CIN
Figure 6a. LTC3406 Suggested Layout
3406 F06a
COUT CIN
Figure 6b. LTC3406-1.8 Suggested Layout
3406 F06b
Design Example
As a design example, assume the LTC3406 is used in a
Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 240mA and f = 1.5MHz in equation (3) gives:
single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of L =
�?= 2.81µH
4.2V down to about 2.7V. The load current requirement
1.5MHz(240mA) �?4.2V �?is a maximum of 0.6A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
A 2.2µH inductor works well for this application. For best efficiency choose a 720mA or greater inductor with less than 0.2�?series resistance.
CIN will require an RMS current rating of at least 0.3A �?ILOAD(MAX)/2 at temperature and COUT will require an ESR
L = 1 V
�?�?VOUT �?of less than 0.25�? In most cases, a ceramic capacitor will
(f)(∆IL )
VIN �?satisfy this requirement.
APPLICATIO S I FOR ATIO
For the feedback resistors, choose R1 = 316k. R2 can then be calculated from equation (2) to be:
R2 = �?VOUT �?1�?R1 = 1000k
Figure 7 shows the complete circuit along with its effi- ciency curve.
�? 0.6 �?VOUT = 2.5V
VIN = 2.7V
VIN = 3.6V
2.2µH*
TO 4.2V
LTC3406
2.5V 80
10µF 75
3406 F07a
10 100 1000
* MURATA LQH32CN2R2M33
** TAIYO YUDEN JMK316BJ106ML
�?TAIYO YUDEN LMK212BJ225MG
OUTPUT CURRENT (mA)
3406 F07b
Figure 7a Figure 7b
TYPICAL APPLICATIO S
Single Li-Ion 1.5V/600mA Regulator for
High Efficiency and Small Footprint
TO 4.2V
LTC3406-1.5 C �?4.7µF CER
3406 TA05
*MURATA LQH32CN2R2M33
**TAIYO YUDEN JMK212BJ475MG
†TAIYO YUDEN JMK316BJ106ML
VOUT = 1.5V
VIN = 2.7V
VIN = 4.2V
100mV/DIV
AC COUPLED
500mA/DIV
100mV/DIV
AC COUPLED
500mA/DIV
VIN = 3.6V
500mA/DIV
VIN = 3.6V VOUT = 1.5V
20µs/DIV
3406 TA07
500mA/DIV
VIN = 3.6V VOUT = 1.5V
20µs/DIV
3406 TA08
10 100 1000
ILOAD = 0A TO 600mA
ILOAD = 200mA TO 600mA
OUTPUT CURRENT (mA)
3406 TA06
TYPICAL APPLICATIO S
Single Li-Ion 1.2V/600mA Regulator for High Efficiency and Small Footprint
2.2µH*
TO 4.2V
LTC3406
3406 TA09
* MURATA LQH32CN2R2M33
** TAIYO YUDEN JMK316BJ106ML
�?TAIYO YUDEN LMK212BJ225MG
VOUT = 1.2V
VIN = 2.7V
VIN = 4.2V VIN = 3.6V
100mV/DIV
AC COUPLED
500mA/DIV
500mA/DIV
100mV/DIV
AC COUPLED
500mA/DIV
500mA/DIV
65 VIN = 3.6V VOUT = 1.2V
20µs/DIV
3406 TA11
VIN = 3.6V VOUT = 1.2V
20µs/DIV
3406 TA12
10 100 1000
ILOAD = 0mA TO 600mA
ILOAD = 200mA TO 600mA
OUTPUT CURRENT (mA)
3406 TA10
Tiny 3.3V/600mA Buck Regulator
2.2µH*
LTC3406
COUT**
3406 TA13
* MURATA LQH32CN2R2M33
** TAIYO YUDEN JMK316BJ106ML
�?TAIYO YUDEN JMK212BJ475MG
VIN = 5V VOUT = 3.3V
100mV/DIV
AC COUPLED
500mA/DIV
75 ILOAD
500mA/DIV
VIN = 5V VOUT = 3.3V
20µs/DIV
3406 TA15
10 100 1000
ILOAD = 200mA TO 600mA
OUTPUT CURRENT (mA)
3406 TA14
PACKAGE DESCRIPTIO
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 �?1.75 (NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.95 BSC
0.30 �?0.45 TYP
5 PLCS (NOTE 3)
0.20 BSC
DATUM ‘A�?0.80 �?0.90
1.00 MAX
0.01 �?0.10
0.30 �?0.50 REF
0.09 �?0.20
1.90 BSC
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
(NOTE 3) S5 TSOT-23 0302
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3406fa
TYPICAL APPLICATIO
Single Li-Ion 1.8V/600mA Regulator for Low Output Ripple and Small Footprint
4.7µH*
TO 4.2V
LTC3406-1.8
3406 TA01
+ COUT1�?*MURATA LQH32CN4R7M34
**TAIYO YUDEN CERAMIC JMK212BJ475MG
†SANYO POSCAP 4TPB100M
VOUT = 1.8V
VIN = 2.7V VIN = 3.6V
100mV/DIV
AC COUPLED
500mA/DIV
100mV/DIV
AC COUPLED
500mA/DIV
VIN = 4.2V
500mA/DIV
500mA/DIV
65 VIN = 3.6V VOUT = 1.8V
40µs/DIV
3406 TA03
VIN = 3.6V VOUT = 1.8V
40µs/DIV
3406 TA04
10 100 1000
ILOAD = 0mA TO 600mA
ILOAD = 200mA TO 600mA
OUTPUT CURRENT (mA)
3406 TA02
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1474/LTC1475 250mA (IOUT) Low Quiescent Current Step-Down VIN: 3V to 18V, Constant Off-Time, IQ = 10µA, MS8 Package
DC/DC Converters
LT1616 1.4MHz, 600mA Step-Down DC/DC Converter VIN: 3.6V to 25V, IQ = 1.9mA, ThinSOT Package
LTC1701 1MHz, 500mA (IOUT) Step-Down DC/DC Converter VIN: 2.5V to 5.5V, Constant Off-Time, IQ = 135µA, ThinSOT Package
LTC1767 1.5A, 1.25MHz Step-Down Switching Regulator VIN: 3V to 25V, IQ = 1mA, MS8/E Packages LTC1779 550kHz, 250mA (IOUT) Step-Down Switching Regulator VIN: 2.5V to 9.8V, IQ = 135µA, ThinSOT Package LTC1875 550kHz, 1.2A (IOUT) Synchronous Step-Down Regulator VIN: 2.7V to 6V, IQ = 15µA, TSSOP-16 Package LTC1877 550kHz, 600mA (IOUT) Synchronous Step-Down Regulator VIN: 2.65V to 10V, IQ = 10µA, MS8 Package LTC1878 550kHz, 600mA (IOUT) Synchronous Step-Down Regulator VIN: 2.65V to 6V, IQ = 10µA, MS8 Package LTC1879 550kHz, 1.2A (IOUT) Synchronous Step-Down Regulator VIN: 2.7V to 10V, IQ = 15µA, TSSOP-16 Package
LTC3404 1.4MHz, 600mA (IOUT) Synchronous Monolithic Up to 95% Efficiency, VIN: 2.65V to 6V, IQ = 10µA, MS8 Package
Step-Down Regulator
LTC3405/LTC3405A 1.5MHz, 300mA (IOUT) Synchronous Monolithic Up to 95% Efficiency, VIN: 2.5V to 5.5V, IQ = 20µA, LTC3405A-1.5 Step-Down Regulators Fixed Output Voltages Available, ThinSOT Package LTC3405A-1.8
LTC3406B 1.5MHz, 600mA (IOUT) Synchronous Monolithic Up to 95% Efficiency, with Pulse Skipping Mode LTC3406B-1.5 Step-Down Regulators Fixed Output Voltages Available, ThinSOT Package LTC3406B-1.8
LTC3411 4MHz, 1.25A (IOUT) Synchronous Monolithic Up to 95% Efficiency, VIN: 2.5V to 5.5V, IQ = 60µA, MS Package
Step-Down Regulator
LTC3412 4MHz, 2.5A (IOUT) Synchronous Monolithic Up to 95% Efficiency, VIN: 2.5V to 5.5V, IQ = 60µA, TSSOP Package
Step-Down Regulator
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
3406fa
LT/TP 0604 1K REV A �?PRINTED IN USA
(408) 432-1900
�? FAX: (408) 434-0507
�?
© LINEAR TECHNOLOGY CORPORATION 2002

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Features
�?Gate drive supply range from 6 to 20V
�?CMOS Schmitt-triggered inputs
Data Sheet No. PD60177 Rev. E
IR4426/IR4427/IR4428(S) & (PbF) DUAL LOW SIDE DRIVER
Product Summary
�?Matched propagation delay for both channels
�?Outputs out of phase with inputs (IR4426)
�?Outputs in phase with inputs (IR4427)
�?OutputA out of phase with inputA and
OutputB in phase with inputB (IR4428)
�?Also available LEAD-FREE
Descriptions
The IR4426/IR4427/IR4428 (S) is a low voltage, high speed power MOSFET and IGBT driver. Pro- prietary latch immune CMOS technologies en- able ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for mini- mum driver cross-conduction. Propagation delays between two channels are matched.
IO+/- 1.5A / 1.5A VOUT 6V - 20V
ton/off (typ.) 85 & 65 ns
Packages
8 Lead PDIP
8 Lead SOIC
Block Diagram
INB OUTB
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to GND. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VS Fixed supply voltage -0.3 25
VO Output voltage -0.3 VS + 0.3
VIN Logic input voltage -0.3 VS + 0.3
PD Package power dissipation @ TA �?+25°C (8 Lead PDIP) �? 1.0 (8 lead SOIC) �?0.625
RthJA Thermal resistance, junction to ambient (8 lead PDIP) �? 125 (8 lead SOIC) �?200
TJ Junction temperature �?150
TS Storage temperature -55 150
TL Lead temperature (soldering, 10 seconds) �?300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND.
Symbol Definition Min. Max. Units
VS Fixed supply voltage 6 20
VO Output voltage 0 VS V VIN Logic input voltage 0 VS
TA Ambient temperature -40 125 °C
DC Electrical Characteristics
VBIAS (VS) = 15V, TA = 25°C unless otherwise specified. The VIN, and IIN parameters are referenced to GND and are applicable to input leads: INA and INB. The VO and IO parameters are referenced to GND and are applicable to the output leads: OUTA and OUTB.
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic �?�?input voltage (OUTA=LO, OUTB=LO) 2.7 �?�?(IR4426)
Logic �?�?input voltage (OUTA=HI, OUTB=HI) V (IR4427)
Logic �?�?input voltage (OUTA=LO), Logic �?�?input voltage (OUTB=HI) (IR4428)
DC Electrical Characteristics cont.
VBIAS (VS) = 15V, TA = 25°C unless otherwise specified. The VIN, and IIN parameters are referenced to GND and are applicable to input leads: INA and INB. The VO and IO parameters are referenced to GND and are applicable to the output leads: OUTA and OUTB.
Symbol Definition Min. Typ. Max. Units Test Conditions
VIL Logic �?�?input voltage (OUTA=HI, OUTB=HI) �?�?0.8 (IR4426)
Logic �?�?input voltage (OUTA=LO, OUTB=LO)
(IR4427)
Logic “I�?input voltage (OUTA=HI), Logic �?�?V
input voltage (OUTB=LO) (IR4428)
VOH High level output voltage, VBIAS-VO �?�?1.2
VOL Low level output voltage, VO �?�?0.1
IIN+ Logic �?�?input bias current (OUT=HI) �? 5 15 VIN = 0V (IR4426) VIN = VS (IR4427) VINA = 0V (IR4428)
VINB = VS (IR4428)
IIN- Logic �?�?input bias current (OUT=LO) �?-10 -30
µA VIN = VS (IR4426) VIN = 0V (IR4427) VINA = VS (IR4428)
VINB = 0V (IR4428)
IQS Quiescent Vs supply current �?100 200 VIN = 0V or VS
IO+ Output high short circuit pulsed current 1.5 2.3 �?VO = 0V, VIN = 0 (IR4426)
VO = 0V, VIN = VS
(IR4427)
VO = 0V, VINA = 0 (IR4428)
VO = 0V, VINB = VS
(IR4428)
A PW �?10 µs
IO- Output low short circuit pulsed current 1.5 3.3 �?VO = 15V, VIN = VS
(IR4426)
VO = 15V, VIN = 0 (IR4427)
VO = 15V, VINA = VS
(IR4428)
VO = 15V, VINB = 0 (IR4428)
PW �?10 µs
AC Electrical Characteristics
VBIAS (VS) = 15V, CL = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
Propagation delay characteristics
td1 Turn-on propagation delay �?85 160
td2 Turn-off propagation delay �?65 150 tr Turn-on rise time �?15 35
tf Turn-off fall time �?10 25
ns figure 4
Functional Block Diagram IR4426
PREDRV DRV
PREDRV DRV
Functional Block Diagram IR4427
PREDRV DRV
PREDRV DRV
Functional Block Diagram IR4428
PREDRV DRV
PREDRV DRV
Lead Definitions Symbol Description VS Supply voltage GND Ground
INA Logic input for gate driver output (OUTA), out of phase (IR4426, IR4428), in phase (IR4427) INB Logic input for gate driver output (OUTB), out of phase (IR4426), in phase (IR4427, IR4428) OUTA Gate drive output A
OUTB Gate drive output B
Lead Assignments
INA GND
VS OUTB
INA GND
VS OUTB
INA GND
VS OUTB
8 Lead PDIP 8 Lead PDIP 8 Lead PDIP
IR4426 IR4427 IR4428
Part Number
Lead Assignments
INA GND
VS OUTB
INA GND
VS OUTB
INA GND
VS OUTB
8 Lead SOIC 8 Lead SOIC 8 Lead SOIC
IR4426S IR4427S IR4428S Part Number
INA (IR4426, IR4428) INB (IR4426)
INA (IR4427)
INB (IR4427, IR4428)
OUTA OUTB
Figure 3. Timing Diagram
INA (IR4426, IR4428) INB (IR4426)
INA (IR4427)
INB (IR4427, IR4428)
td2 tf
OUTA OUTB
Figure 4. Switching Time Waveforms
VS = 15V
VS = 15V
6 4.7UF 0.1UF
6 4.7UF 0.1UF
CL = 1000PF
CL = 1000PF
CL = 1000PF
CL = 1000PF
3 VS = 15V 3
6 4.7UF 0.1UF
IR4427
CL = 1000PF
OUTB CL = 1000PF
Figure 5. Switching Time Test Circuits
Caseoutline
8 Lead PDIP 01-3003 01
Tape & Reel
Case Outline - 8 Lead SOIC
(MS-012AA) 01-0021 09
LEADFREE PART MARKING INFORMATION
Part number
Date code
Identifier
IRxxxxxx
IR logo
Lot Code
? MARKING CODE
P Lead Free Released Non-Lead Free Released
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
Basic Part (Non-Lead Free)
8-Lead PDIP IR4426 order IR4426
8-Lead SOIC IR4426S order IR4426S
8-Lead PDIP IR4427 order IR4427
8-Lead SOIC IR4427S order IR4427S
8-Lead PDIP IR4428 order IR4428
8-Lead SOIC IR4428S order IR4428S
Leadfree Part
8-Lead PDIP IR4426 order IR4426PbF
8-Lead SOIC IR4426S order IR4426SPbF
8-Lead PDIP IR4427 order IR4427PbF
8-Lead SOIC IR4427S order IR4427SPbF
8-Lead PDIP IR4428 order IR4428PbF
8-Lead SOIC IR4428S order IR4428SPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been qualified per industrial level
Data and specifications subject to change without notice. 4/13/2004

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ThOMSON - EFCIS
Integrated Circuits
AF AMPLIFIER AMPLIFICATEUR BF
The TCA 940,E is a monolithic integreted circuit designed for class B audio amplification, with up to 10 W output power.
It provides all the advantages of integrated AF amplifiers: constant idling current and voltage, high efficiency, low distortion; furthermore, an internal circuit protects it against overheating, supply overvoltage and load
short-circuit.
The TCA g4o, E is pin-to-pin compatible with TBA 810 AS.
Le TCA 940, 5 est un circuit monolithique destine a I’amplification BF classe
B, sa puissance he sortie peut atteindre lOW.
II presente bus es avantages des amplificateurs BF inthgrds stabilité du courant et de a tension he repos, rendement hleué, faible distorsion, en outre, un dispositif intérieur In protege contre I’échauffement excessif. les uurtenuions d’afimentation et le court-circuit he Ia charge
Le TCA 940, E est interchangeable broche a broche avec le TBA 810 AS
TCA94O TCA94O E
AF AMPLIFIER AMPLIFICATEUR BF
CASES / BOITIERS
TCA 940
TCA 940 E
BLOCK DIAGRAM SCHEMA ELECTRIQUE
PLASTIC PACKAGES BOITIERS PLASTIQIJE
PIN CONFIGURATION BROCHAGE
Oil 6:2
r I 02c
L’m tnu
04 06
AS . 013 �?05 06 /5/
7 Pse.mpliltsr as000pitna
Secouniogo do
1 °cc proomri,licaiour
2 Not to use 5 input Enirao
No put oil/SOt 5 substrete.sd
3 Not to use posempht.sr a0000d
Lo. �?5
04 c,�?oo
No put ouSter Subsiruini motto
4 Sootuttep do prAampi,ttcuiour
Bootstrap 10 Ootput ete5s as000d
S cnosst,o Maoot do idiugo
Comporisat’oA
5 Foea.bsok network 11 Not to use
No positltittor
Atsouu do conrrorouccon
12 Output Sort
lob mutt be grounded
ThOMSONEFCIS
Sales headquarters
45, au ae i’Euroeo - 7tt40 VELIZY - FRANCE
3d. 1319469719 / Toieu 204790 F
NT7341 119
iii’�?1111110 I1IOMSON—cSF
ilIllIlli
Maximum power dissipation
TCA 940 Dissipationdepuissancemaximafe TeA 940 F
Pt01 Plot
(WI (WI
(1 With infinite heat sink
4 Arec radiates, infin, 4
3 (2) With a 10°C/W heat sink
Ares radiateur d.n 1O°CJW
(3) Without heat sink 2
Sans radiateur
0 25 513 75 lOG 125 TbC( 0 25 50 75 100 325
LIMITING VALUES
VALEURS LIMITES ABSOLUES
Supply eoltage V
Tens,c., d’elin,entat,on CC
Peak output current (non repetitive) I 3 5 A
Cou rant c,Cte en sortie nan ,épët,ti( 0
Peak output current (repetitive) I 3
Can rant crete en sortie répét,tif 0
Junction temperature T. �?0
flmpéiiture dejonction I I- 150
Storage temperature T �?0
Tempémture de stockag stg -1150
ELECTR CAL CHARACTER ISTICS (Note 1) (Unless otherwise stated)
CARACTER(STIQUES ELECTRIQUES (Saul indications consraires)
Test conditions Typ.
Conditions de mesure
Supply soltage 6 24
Tension d’alimentasion
Quiescent output noltage (pin 12) �? ts V
Tension do iepos (fsrnche t2)
Quiescent current isV 20 42 mA
Courantde repos
Bias current (pin 8) �? isv I 0,5 3 MA
Cnajrant d’entree (broche 81
RL _U P0 10 w
I —tkl-Iz
V = 20 V
Output power
t �?kHz
�? 18 V
ci =10%
7 9 W
Puissance do sortie L U 7
$ �?kHz
V �? 16 V
ci =10%
AL U 6,5 iv f �?kHz
�? 20 V
f =1kHz
Vcc = iSV
Voltage for input saturation (peak)
Tension saturanr i’entres (thte) V1 250 wV
P0 -9W
vcc isv
Sensitiuity AL �? 4 U 90 wV
Sensibilite I �? 1 kHo
Input impedance (pinS)
lmpd dance d’enrrée (broche 8)
Note 1 . The characteristics abone were obtained using the circuit shown in figure 1
Megirh dans los conditions de Ia ligcrr
THOMSON-EFCIS Integrated Circuits
ELECTRICAL CHARACTERISTICS
CARACTERISTIO(JES ELECTRIQUES amb
Test conditions
Conditions de mesure
Unless otherwise stated)
(Said ind,cations con traires)
Mw. Typ. Max.
Frequency response (�? dB(
Bande passanre (�? siB)
= 18V
C3 = l000pF
40-20000 Hz
P0 =5OmW° Distortion 5W
D,storuon RL d
f �?kHz
Voltage gain (open loop)
Gain tension en boo etc onverte
Voltage gain (closed loop)
Gain de tension en boucle fermée
Input noise voltage
Teteion sic bruit a
Input noise current
Coo rant de bruit a l’ent,Pe
= 18 V
f =1kHz
Rf =560
f =1kHz
B(�?d8) =40 Vn
20000 Hz
Vcc = 18 V
B (�? dB( = 40- I
20000 Hz
34 37 40 dB
0,15 nA
tticiency
Renden,ent
Supply voltage rejection
Rejecr,on sic !ondolar,res d’alimentatio,,
THERMAL CHARACTERISTICS
CA RACTERISTIQUES THERMIQUES
Junction-case thermal resistance
Résistance thermique (jonctionboitir)
Junction-ambient thermal resistance
Résistance rhermique (jonct,onambiante)
P0 =9W
Vcc 18V
ripple = 100Hz
Rth(jc( Rth(ja(
80 cciw
ELECTRICAL CHARACTERISTICS (Unless otherwise stated(
CARACTERISTIQUES ELECTRIQUES Tamb = 25°C (Saul indications contraires)
Test conditions
Conditions de mesure
Supply voltage
Tension dal,mentation 6 24 V
Quiescent output voltage (pin 12(
Tension de repos (broche 52) �? 18 V VQ 8,2 9 9,8 V
Quiescent current (pin 1
Courantderepos (broche 1) = iSV ICC 20 42 mA
Bias current (pin 8(
Couranrd’entrée (broche8) VCC = 18 V I 0,5 3
Output power
Puissance de sortie
d =10%
f = 1 kHz PQ 5,5 W
VCC = 20V
ii =10%
RL =8f2 54
f =1kHz
VCC = iSV
Voltage for input saturation (peak(
Tension saturantl’entrée (crete) V1 250 mV
P0 =5,4W Sensitivity VCC = 18 V
Sensibihté = 8 !2 S 90 mV
f =1kHz
Rf =560
Input iwpedance (pin 8(
Impédance d’entrée (broche 8)
Frequency response (�? dB( VCC = 18 V 8 40-20000 Hz
Bande passante (�? dB) C3 = 1000 pF
Note 1 The characteristics above were obtained using the circuit shown in figure 1
Mesure dans leo conditions de Ia Figore I
11-IOMSON-EFCIS Integrated Circuits
ELECTRICAL CHARACTERISTICS
CARACTERIST/QUES EL ECTRIQUES Tamb
Unless otherwise stated)
(Saufind,carions con trait-es)
Test conditions Miii. Typ. Max.
Conditions de mesure
�? 18V
P0 =50mW-. Distorsion 3,5 W Distot-sion R L =
Rf 5622
f =1kHz
d 0,2 %
Voltage gain )open loop) Vcc = 18 V
Gain de tension en boucle R L = 8 Q Av 75 dB
f = 1kHz
= 18V Voltage gain closed loop) RL = 8 E2
Gain de tension en boucle fe,mée = 56 0
f = 1kHz
Input noise voltage
Tension de bruit è I’entrée I
Vcc 18V
B)�? dB) 40 - V 3
I 20000Hz
Input noise current Vcc 18 V
Courantdebru,tài’ent,-ée B(�? dB) = 40- In 0,15 nA
20 000 Hz
Vcc = 18V Efficiency P0 = 5,4 W Rendenient
RL = 80
f =1kHz
Supply voltage rejection
Rejection de I’ondulation d’a!in,entation
Vcc = iSV
RL = 8 SVR 43 riB
ripple = 100 Hz
THERMAL CHARACTERISTICS
CARACTERIST/QUES THERM/DUES
Junction-case thermal resistance
Résistance thermique (/oncrion-boit,er) Rth)jc) 12 °C/W
Junction•srnbient thermal resistance
Résistance therm ique (jonction-arnbiante) Rth)Ia) 70* °C/W
* Tabs soldered to printed Circuit with minimized copper area
Ailettes soudées au circuit imprimf evec use surface de cuivre réduite
THOMSON-EFCIS Integrated Circuits
MEASUREMENT AND APPLICATION DIAGRAM
SCHEMA D’APPL!CATIQN ETDE MESUHE
01 100pF
aT aT15V
Tabs 12
At TCA94O,E
1000 0F
lOOeF 4700pF O1sF /a> datasheet
TCA940 circuit
TCA940 pinout
TCA940 transistor
ThOMSON - EFCIS
Integrated Circuits
AF AMPLIFIER AMPLIFICATEUR BF
The TCA 940,E is a monolithic integreted circuit designed for class B audio amplification, with up to 10 W output power.
It provides all the advantages of integrated AF amplifiers: constant idling current and voltage, high efficiency, low distortion; furthermore, an internal circuit protects it against overheating, supply overvoltage and load
short-circuit.
The TCA g4o, E is pin-to-pin compatible with TBA 810 AS.
Le TCA 940, 5 est un circuit monolithique destine a I’amplification BF classe
B, sa puissance he sortie peut atteindre lOW.
II presente bus es avantages des amplificateurs BF inthgrds stabilité du courant et de a tension he repos, rendement hleué, faible distorsion, en outre, un dispositif intérieur In protege contre I’échauffement excessif. les uurtenuions d’afimentation et le court-circuit he Ia charge
Le TCA 940, E est interchangeable broche a broche avec le TBA 810 AS
TCA94O TCA94O E
AF AMPLIFIER AMPLIFICATEUR BF
CASES / BOITIERS
TCA 940
TCA 940 E
BLOCK DIAGRAM SCHEMA ELECTRIQUE
PLASTIC PACKAGES BOITIERS PLASTIQIJE
PIN CONFIGURATION BROCHAGE
Oil 6:2
r I 02c
L’m tnu
04 06
AS . 013 �?05 06 /5/
7 Pse.mpliltsr as000pitna
Secouniogo do
1 °cc proomri,licaiour
2 Not to use 5 input Enirao
No put oil/SOt 5 substrete.sd
3 Not to use posempht.sr a0000d
Lo. �?5
04 c,�?oo
No put ouSter Subsiruini motto
4 Sootuttep do prAampi,ttcuiour
Bootstrap 10 Ootput ete5s as000d
S cnosst,o Maoot do idiugo
Comporisat’oA
5 Foea.bsok network 11 Not to use
No positltittor
Atsouu do conrrorouccon
12 Output Sort
lob mutt be grounded
ThOMSONEFCIS
Sales headquarters
45, au ae i’Euroeo - 7tt40 VELIZY - FRANCE
3d. 1319469719 / Toieu 204790 F
NT7341 119
iii’�?1111110 I1IOMSON—cSF
ilIllIlli
Maximum power dissipation
TCA 940 Dissipationdepuissancemaximafe TeA 940 F
Pt01 Plot
(WI (WI
(1 With infinite heat sink
4 Arec radiates, infin, 4
3 (2) With a 10°C/W heat sink
Ares radiateur d.n 1O°CJW
(3) Without heat sink 2
Sans radiateur
0 25 513 75 lOG 125 TbC( 0 25 50 75 100 325
LIMITING VALUES
VALEURS LIMITES ABSOLUES
Supply eoltage V
Tens,c., d’elin,entat,on CC
Peak output current (non repetitive) I 3 5 A
Cou rant c,Cte en sortie nan ,épët,ti( 0
Peak output current (repetitive) I 3
Can rant crete en sortie répét,tif 0
Junction temperature T. �?0
flmpéiiture dejonction I I- 150
Storage temperature T �?0
Tempémture de stockag stg -1150
ELECTR CAL CHARACTER ISTICS (Note 1) (Unless otherwise stated)
CARACTER(STIQUES ELECTRIQUES (Saul indications consraires)
Test conditions Typ.
Conditions de mesure
Supply soltage 6 24
Tension d’alimentasion
Quiescent output noltage (pin 12) �? ts V
Tension do iepos (fsrnche t2)
Quiescent current isV 20 42 mA
Courantde repos
Bias current (pin 8) �? isv I 0,5 3 MA
Cnajrant d’entree (broche 81
RL _U P0 10 w
I —tkl-Iz
V = 20 V
Output power
t �?kHz
�? 18 V
ci =10%
7 9 W
Puissance do sortie L U 7
$ �?kHz
V �? 16 V
ci =10%
AL U 6,5 iv f �?kHz
�? 20 V
f =1kHz
Vcc = iSV
Voltage for input saturation (peak)
Tension saturanr i’entres (thte) V1 250 wV
P0 -9W
vcc isv
Sensitiuity AL �? 4 U 90 wV
Sensibilite I �? 1 kHo
Input impedance (pinS)
lmpd dance d’enrrée (broche 8)
Note 1 . The characteristics abone were obtained using the circuit shown in figure 1
Megirh dans los conditions de Ia ligcrr
THOMSON-EFCIS Integrated Circuits
ELECTRICAL CHARACTERISTICS
CARACTERISTIO(JES ELECTRIQUES amb
Test conditions
Conditions de mesure
Unless otherwise stated)
(Said ind,cations con traires)
Mw. Typ. Max.
Frequency response (�? dB(
Bande passanre (�? siB)
= 18V
C3 = l000pF
40-20000 Hz
P0 =5OmW° Distortion 5W
D,storuon RL d
f �?kHz
Voltage gain (open loop)
Gain tension en boo etc onverte
Voltage gain (closed loop)
Gain de tension en boucle fermée
Input noise voltage
Teteion sic bruit a
Input noise current
Coo rant de bruit a l’ent,Pe
= 18 V
f =1kHz
Rf =560
f =1kHz
B(�?d8) =40 Vn
20000 Hz
Vcc = 18 V
B (�? dB( = 40- I
20000 Hz
34 37 40 dB
0,15 nA
tticiency
Renden,ent
Supply voltage rejection
Rejecr,on sic !ondolar,res d’alimentatio,,
THERMAL CHARACTERISTICS
CA RACTERISTIQUES THERMIQUES
Junction-case thermal resistance
Résistance thermique (jonctionboitir)
Junction-ambient thermal resistance
Résistance rhermique (jonct,onambiante)
P0 =9W
Vcc 18V
ripple = 100Hz
Rth(jc( Rth(ja(
80 cciw
ELECTRICAL CHARACTERISTICS (Unless otherwise stated(
CARACTERISTIQUES ELECTRIQUES Tamb = 25°C (Saul indications contraires)
Test conditions
Conditions de mesure
Supply voltage
Tension dal,mentation 6 24 V
Quiescent output voltage (pin 12(
Tension de repos (broche 52) �? 18 V VQ 8,2 9 9,8 V
Quiescent current (pin 1
Courantderepos (broche 1) = iSV ICC 20 42 mA
Bias current (pin 8(
Couranrd’entrée (broche8) VCC = 18 V I 0,5 3
Output power
Puissance de sortie
d =10%
f = 1 kHz PQ 5,5 W
VCC = 20V
ii =10%
RL =8f2 54
f =1kHz
VCC = iSV
Voltage for input saturation (peak(
Tension saturantl’entrée (crete) V1 250 mV
P0 =5,4W Sensitivity VCC = 18 V
Sensibihté = 8 !2 S 90 mV
f =1kHz
Rf =560
Input iwpedance (pin 8(
Impédance d’entrée (broche 8)
Frequency response (�? dB( VCC = 18 V 8 40-20000 Hz
Bande passante (�? dB) C3 = 1000 pF
Note 1 The characteristics above were obtained using the circuit shown in figure 1
Mesure dans leo conditions de Ia Figore I
11-IOMSON-EFCIS Integrated Circuits
ELECTRICAL CHARACTERISTICS
CARACTERIST/QUES EL ECTRIQUES Tamb
Unless otherwise stated)
(Saufind,carions con trait-es)
Test conditions Miii. Typ. Max.
Conditions de mesure
�? 18V
P0 =50mW-. Distorsion 3,5 W Distot-sion R L =
Rf 5622
f =1kHz
d 0,2 %
Voltage gain )open loop) Vcc = 18 V
Gain de tension en boucle R L = 8 Q Av 75 dB
f = 1kHz
= 18V Voltage gain closed loop) RL = 8 E2
Gain de tension en boucle fe,mée = 56 0
f = 1kHz
Input noise voltage
Tension de bruit è I’entrée I
Vcc 18V
B)�? dB) 40 - V 3
I 20000Hz
Input noise current Vcc 18 V
Courantdebru,tài’ent,-ée B(�? dB) = 40- In 0,15 nA
20 000 Hz
Vcc = 18V Efficiency P0 = 5,4 W Rendenient
RL = 80
f =1kHz
Supply voltage rejection
Rejection de I’ondulation d’a!in,entation
Vcc = iSV
RL = 8 SVR 43 riB
ripple = 100 Hz
THERMAL CHARACTERISTICS
CARACTERIST/QUES THERM/DUES
Junction-case thermal resistance
Résistance thermique (/oncrion-boit,er) Rth)jc) 12 °C/W
Junction•srnbient thermal resistance
Résistance therm ique (jonction-arnbiante) Rth)Ia) 70* °C/W
* Tabs soldered to printed Circuit with minimized copper area
Ailettes soudées au circuit imprimf evec use surface de cuivre réduite
THOMSON-EFCIS Integrated Circuits
MEASUREMENT AND APPLICATION DIAGRAM
SCHEMA D’APPL!CATIQN ETDE MESUHE
01 100pF
aT aT15V
Tabs 12
At TCA94O,E
1000 0F
lOOeF 4700pF O1sF [( L
lOOstF 122
Figure 1
*CE = SOOpF —l5voltspour RL822
CE 1000?IF_l5voItspourRL4U
OVERLOAD AND OVERVOLTAGE PROTECTION
PROTECTION CONTRE U’S SLIRCHA ROES ET LEE StIR TENSIONS
Each power transistor is protected by a special, entirely integrated circuit which prevents it from working in dangerous conditions. The permitted area will not shrink with increased junction temperature.
Cheque rressaisror de puisuaece eer prorege par an circair special, enriCrewenr inrégre, qai l’ewpéche do foecrionner dew des conditions dangereuaes. L’eii-e parwiae Ce rerrécit gas qaavd (a tewperarare de joncrioe aagweeta
TCApeOE Al
TCA 940
Perwissed area leach tracsistorl Aire perwiae a chaque craeaiaror
2�? I
&o&echee
RL 812
Perwissed arei/�?leach sransissor
.4ire perwiue a
cheque rransiuror
Load line
0 5 10 15 20
0 5 10 15 20
THERMAL PROTECTION
SECURI TE THERMIOUE
When the die is overheated, available output current progressively falls down to 0.
Cooed Ia pearl/fe ieregree s’échaaffe rrep, le cearanr disponible cc serrie rowbe progressiuewenr a 0.
0 50 100 T.
THOMSON-EFCIS Integrated Circuits
CASE/BOITIER CB-109
l 1,r PLASTIC PACKAGE
noupu+2b.i,.k BOtTlER PLASTIQUE
j_ asiC [SITiiiSc 1HOMSON-ErCi
l542S4 762 _TTtii stZ21o7_
3_si *3,51
7 tri I �?I 035 L.J�? SO-nj
4 CASE /BOITIER CE-i
T ooa pus
P LAST IC PAC KAGE
435 BOtTlER PLASTIQUE
CS -155
CDI 0012 JE5EC 5iTCLrsC THOMSON EFCiS
These specifications are subject to change without notice.
Please inquire with our sales offices about the asailability of the different packages.

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Ultra Fast Avalanche Sinterglass Diode
Features
�? Glass passivated junction
�? Hermetically sealed package e2
�? Very low switching losses
�? Low reverse current
�? High reverse voltage
�? Lead (Pb)-free component
�? Component in accordance to RoHS 2002/95/EC
and WEEE 2002/96/EC
Applications
Switched mode power supplies
High-frequency inverter circuits
Mechanical Data
Case: SOD-57 Sintered glass case
Terminals: Plated axial leads, solderable per
MIL-STD-750, Method 2026
Polarity: Color band denotes cathode end
Mounting Position: Any
Weight: approx. 369 mg
Parts Table
Part Type differentiation Package
BYV26A VR = 200 V; IFAV = 1 A SOD-57
BYV26B VR = 400 V; IFAV = 1 A SOD-57
BYV26C VR = 600 V; IFAV = 1 A SOD-57
BYV26D VR = 800 V; IFAV = 1 A SOD-57
BYV26E VR = 1000 V; IFAV = 1 A SOD-57
Absolute Maximum Ratings
Tamb = 25 °C, unless otherwise specified
Parameter Test condition Part Symbol Value Unit
Reverse voltage = Repetitive peak reverse voltage
see electrical characteristics BYV26A VR = VRRM 200 V
BYV26B VR = VRRM 400 V BYV26C VR = VRRM 600 V BYV26D VR = VRRM 800 V
BYV26E VR = VRRM 1000 V
Peak forward surge current tp = 10 ms, half sinewave IFSM 30 A Average forward current IFAV 1 A
Non repetitive reverse avalanche energy
Junction and storage temperature range
I(BR)R = 1 A, inductive load ER 10 mJ Tj = Tstg - 55 to + 175 °C
Maximum Thermal Resistance
Tamb = 25 °C, unless otherwise specified
Parameter Test condition Symbol Value Unit
Junction ambient l = 10 mm, TL = constant RthJA 45 K/W
Electrical Characteristics
Tamb = 25 °C, unless otherwise specified
Parameter Test condition Part Symbol Min Typ. Max Unit
Forward voltage IF = 1 A VF 2.5 V IF = 1 A, Tj = 175 °C VF 1.3 V
Reverse current VR = VRRM IR 5 µA VR = VRRM, Tj = 150 °C IR 100 µA
Reverse breakdown voltage IR = 100 µA BYV26A V(BR)R 300 V BYV26B V(BR)R 500 V BYV26C V(BR)R 700 V BYV26D V(BR)R 900 V
BYV26E V(BR)R 1100 V
Reverse recovery time IF = 0.5 A, IR = 1 A, iR = 0.25 A BYV26A- BYV26C
BYV26D- BYV26E
trr 30 ns
trr 75 ns
Typical Characteristics (Tamb = 25 °C unless otherwise specified)
RthJA = 45 K/W
RthJA= 100 K/W
VR = VRRM
VR = VRRM
0 40 80 120
0 40 80 120 16° 0 200
95 9728
Tj �?Junction Temperature ( C)
95 9729
Tj �?Junction Temperature ( C)
Figure 1. Max. Reverse Power Dissipation vs. Junction
Temperature
Figure 2. Max. Reverse Current vs. Junction Temperature
RthJA = 45 K/W
35 f = 1 MHz
95 9730
RthJA = 100 K/W
0 40 80 120 16°0
Tamb - Ambient Temperature ( C)
0.1 1 10 100
VR - Reverse Voltage ( V )
Figure 3. Max. Average Forward Current vs. Ambient Temperature
Figure 5. Diode Capacitance vs. Reverse Voltage
Tj =175 C
Tj = 25 C
35 f = 1 MHz
25 BYV26E
0.01 10
95 9731
1 2 3 5 6 6 7
VF - Forward Voltage(V)
0.1 1 10 100
VR - Reverse Voltage ( V )
Figure 4. Max. Forward Current vs. Forward Voltage
Figure 6. Diode Capacitance vs. Reverse Voltage
Package Dimensions in mm (Inches)
Sintered Glass Case
Cathode Identification
3.6 (0.140)max.
ISO Method E
94 9538
0.82 (0.032) max.
26(1.014) min.
4.0 (0.156) max.
26(1.014) min.
Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.
Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.
Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Legal Disclaimer Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000
Revision: 08-Apr-05 1

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Single chip 2.4 GHz Transceiver
nRF2401A
FEATURES APPLICATIONS
�? True single chip GFSK transceiver in a small
24-pin package (QFN24 5x5mm)
�?Wireless mouse, keyboard, joystick
�? Keyless entry
�? Data rate 0 to1Mbps �? Wireless data communication
�? Only 2 external components �? Alarm and security systems
�?Multi channel operation
�?125 channels
�?Channel switching time <200s.
�?Support frequency hopping
�?Home automation
�?Surveillance
�?Automotive
�? Data slicer / clock recovery of data �? Telemetry
�? Address and CRC computation �? Intelligent sports equipment
�? DuoCeiver�?for simultaneous dual receiver topology
�? ShockBurst�?mode for ultra-low power operation and relaxed MCU performance
�?Power supply range: 1.9 to 3.6 V
�?Low supply current (TX), typical 10.5mA peak
@ -5dBm output power
�?Low supply current (RX), typical 18mA peak in receive mode
�?100 % RF tested
�?No need for external SAW filter
�?World wide use
GENERAL DESCRIPTION
�? Industrial sensors
�? Toys
nRF2401A is a single-chip radio transceiver for the world wide 2.4 - 2.5 GHz ISM band. The transceiver consists of a fully integrated frequency synthesizer, a power amplifier, a crystal oscillator and a modulator. Output power and frequency channels are easily programmable by use of the 3-wire serial interface. Current consumption is very low, only 10.5mA at an output power of -5dBm and 18mA in receive mode. Built-in Power Down modes makes power saving easily realizable.
QUICK REFERENCE DATA
Parameter Value Unit Minimum supply voltage 1.9 V Maximum output power 0 dBm Maximum data rate 1000 kbps Supply current in transmit @ -5dBm output power 10.5 mA Supply current in receive mode 18 mA Temperature range -40 to +85 C Sensitivity -93 dBm Supply current in Power Down mode 400 nA
Table 1 nRF2401A quick reference data
Type Number Description Version NRF2401A 24 pin QFN 5x5 A NRF2401AG 24 pin QFN 5x5, lead free (green) A
NRF2401A-EVKIT Evaluation kit (2 test PCB, 2 configuration PCB, SW) 1.0
Table 2 nRF2401A ordering information
BLOCK DIAGRAM
DuoCeiverTM
ShockBurstTM
Channel 2
Channel 1
DATA CLK1
DEMOD Clock
Recovery, DataSlicer ADDR Decode CRC
Code/Decode FIFO In/Out
Frequency
Synthesiser
VSS_PA=0V VDD_PA=1.8V
3-wire interface
PA 400�?Figure 1 nRF2401A with external components.
PIN FUNCTIONS
Pin Name Pin function Description
1 CE Digital Input Chip Enable Activates RX or TX mode
2 DR2 Digital Output RX Data Ready at Data Channel 2 (ShockBurst�?only)
3 CLK2 Digital I/O Clock Output/Input for RX Data Channel 2
4 DOUT2 Digital Output RX Data Channel 2
5 CS Digital Input Chip Select Activates Configuration Mode
6 DR1 Digital Output RX Data Ready at Data Channel 1 (ShockBurst�?only)
7 CLK1 Digital I/O Clock Input (TX) & Output/Input (RX) for Data Channel 1
3-wire interface
8 DATA Digital I/O RX Data Channel 1/TX Data Input/ 3-wire interface
9 DVDD Power Output Positive Digital Supply output for de-coupling purposes
10 VSS Power Ground (0V)
11 XC2 Analog Output Crystal Pin 2
12 XC1 Analog Input Crystal Pin 1
13 VDD_PA Power Output Power Supply (+1.8V) to Power Amplifier
14 ANT1 RF Antenna interface 1
15 ANT2 RF Antenna interface 2
16 VSS_PA Power Ground (0V)
17 VDD Power Power Supply (+3V DC)
18 VSS Power Ground (0V)
19 IREF Analog Input Reference current
20 VSS Power Ground (0V)
21 VDD Power Power Supply (+3V DC)
22 VSS Power Ground (0V)
23 PWR_UP Digital Input Power Up
24 VDD Power Power Supply (+3V DC)
Table 3 nRF2401A pin function
PIN ASSIGNMENT
PWR_UP
24 23 22 21
CE 1 18
nRF2401A
CLK2 3
QFN24 5x5
17 VDD
16 VSS_PA
14 ANT1
13 VDD_PA
XC2 XC1
Figure 2 nRF2401A pin assignment (top view) for a QFN24 5x5 package.
ELECTRICAL SPECIFICATIONS
Conditions: VDD = +3V, VSS = 0V, TA = - 40ºC to + 85ºC
Symbol Parameter (condition) Notes Min. Typ. Max. Units
Operating conditions
VDD Supply voltage 1.9 3.0 3.6 V TEMP Operating Temperature -40 +27 +85 ºC
Digital input pin
VIH HIGH level input voltage VDD- 0.3 VDD V VIL LOW level input voltage Vss 0.3 V
Digital output pin
VOH HIGH level output voltage (IOH=-0.5mA) VDD- 0.3 VDD V VOL LOW level output voltage (IOL=0.5mA) Vss 0.3 V
General RF conditions
fOP Operating frequency 1) 2400 2524 MHz fXTAL Crystal frequency 2) 4 20 MHz f Frequency deviation ±156 kHz RGFSK Data rate ShockBurst�? >0 1000 kbps RGFSK Data rate Direct Mode 3) 250 1000 kbps
FCHANNEL Channel spacing 1 MHz
Transmitter operation
PRF Maximum Output Power 4) 0 +4 dBm PRFC RF Power Control Range 16 20 dB PRFCR RF Power Control Range Resolution ±3 dB PBW 20dB Bandwidth for Modulated Carrier 1000 kHz PRF2 2nd Adjacent Channel Transmit Power 2MHz -20 dBm PRF3 3rd Adjacent Channel Transmit Power 3MHz -40 dBm IVDD Supply current @ 0dBm output power 5) 13 mA IVDD Supply current @ -20dBm output power 5) 8.8 mA
IVDD Average Supply current @ -5dBm output power, ShockBurst�?6) 0.8 mA
IVDD Average Supply current in stand-by mode 7) 12 A IVDD Average Supply current in power down 400 nA
Receiver operation
IVDD Supply current one channel 250kbps 18 mA IVDD Supply current one channel 1000kbps 19 mA IVDD Supply current two channels 250kbps 23 mA IVDD Supply current two channels 1000kbps 25 mA RXSENS Sensitivity at 0.1%BER (@250kbps) -93 dBm RXSENS Sensitivity at 0.1%BER (@1000kbps) -85 dBm C/ICO C/I Co-channel 8) 10/4 dB C/I1ST 1st Adjacent Channel Selectivity C/I 1MHz 8) -20/0 dB C/I2ND 2nd Adjacent Channel Selectivity C/I 2MHz 8) -37/-20 dB C/I3RD 3rd Adjacent Channel Selectivity C/I 3MHz 8) -43/-30 dB RXB Blocking Data Channel 2 -45/-41 dB
1) Usable band is determined by local regulations
2) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in the configuration word, see Table 8. 16MHz are required for 1Mbps operation.
3) Data rate must be either 250kbps or 1000kbps.
4) Antenna load impedance = 100�?j175�?5) Antenna load impedance = 100�?j175�? Effective data rate 250kbps or 1Mbps.
6) Antenna load impedance = 100�?j175�? Effective data rate 10kbps.
7) Current if 4 MHz crystal is used.
8) 250kbps/1000kbps.
Table 4 nRF2401A RF specifications
PACKAGE OUTLINE
nRF2401AG uses the GREEN QFN24 5x5 package, with matt tin plating.
nRF2401A uses the QFN24 5x5 package, with SnPb plating. Dimensions are in mm.
Package Type A A1 A2 b D/E D1/E1 e J K L R
Punch QFN24
(5x5 mm)
typ. Max
5 BSC 4.75
0.65 BSC
Figure 3 nRF2401AG GREEN Package outline.
Absolute Maximum Ratings
Supply voltages
VDD ............................ - 0.3V to + 3.6V
VSS .................................................. 0V
Input voltage
VI ....................... - 0.3V to VDD + 0.3V
Output voltage
VO ...................... - 0.3V to VDD + 0.3V
Total Power Dissipation
PD (TA=85C) ............................. 90mW
Temperatures
Operating Temperature�? - 40C to + 85C Storage Temperature�?�?- 40C to + 125C
Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device.
ATTENTION! Electrostatic Sensitive Device Observe Precaution for handling.
Glossary of Terms
Term Description
CLK Clock
CRC Cyclic Redundancy Check
CS Chip Select CE Chip Enable DR Data Ready
GFSK Gaussian Frequency Shift Keying
ISM Industrial-Scientific-Medical
MCU Micro controller OD Overdrive PWR_DWN Power Down PWR_UP Power Up
RX Receive
ST_BY Standby
TX Transmit
Table 5 Glossary
MODES OF OPERATION
Overview
The nRF2401A can be set in the following main modes depending on three control pins:
Mode PWR_UP CE CS
Active (RX/TX) 1 1 0
Configuration 1 0 1
Stand by 1 0 0
Power down 0 X X
Table 6 nRF2401A main modes
For a complete overview of the nRF2401A I/O pins in the different modes please refer to Table 7.
Active modes
The nRF2401A has two active (RX/TX) modes:
�?ShockBurst�?�?Direct Mode
The device functionality in these modes is decided by the content of a configuration word. This configuration word is presented in configuration section.
ShockBurst�?The ShockBurst�?technology uses on-chip FIFO to clock in data at a low data rate and transmit at a very high rate thus enabling extremely power reduction.
When operating the nRF2401A in ShockBurst�? you gain access to the high data rates (1 Mbps) offered by the 2.4 GHz band without the need of a costly, high-speed micro controller (MCU) for data processing.
By putting all high speed signal processing related to RF protocol on-chip, the nRF2401A offers the following benefits:
�?Highly reduced current consumption
�?Lower system cost (facilitates use of less expensive micro controller)
�?Greatly reduced risk of ‘on-air�?collisions due to short transmission time
The nRF2401A can be programmed using a simple 3-wire interface where the data rate is decided by the speed of the micro controller.
By allowing the digital part of the application to run at low speed while maximizing the data rate on the RF link, the nRF ShockBurst�?mode reduces the average current consumption in applications considerably.
ShockBurst�?principle
When the nRF2401A is configured in ShockBurst�? TX or RX operation is conducted in the following way (10 kbps for the example only).
Continuous 10kbps
nRF2401A
ShockBurstTM
Figure 4 Clocking in data with MCU and sending with ShockBurst�?technology
Without ShockBurstTM, running at speed dictated by 10Kbs MCU
10mA periode
10mA period
10Kbs MCU with ShockBurstTM
0 20 40 60 80 100 120 140 160 180 200 220 240
Time mS
Figure 5 Current consumption with & without ShockBurst�?technology
nRF2401A in NO ShockBurstTM
TX (CE=hi)?
uController Loading ADDR and PAYLOAD data
Data content of registers:
ADDR PAYLOAD
Maximum 256 bits
nRF2401A Calculating CRC
ADDR PAYLOAD CRC
CE=Low?
nRF2401A Adding Preamble
Pre- amble
ADDR PAYLOAD CRC
nRF2401A Sending ShockBurstTM Package
(250 or 1000kbps)
Input FIFO not Empty
YES NO Sending
completed?
Figure 6 Flow Chart ShockBurst�?Transmit of nRF2401A
nRF2401A ShockBurst�?Transmit:
MCU interface pins: CE, CLK1, DATA
1. When the application MCU has data to send, set CE high. This activates nRF2401A on-board data processing.
2. The address of the receiving node (RX address) and payload data is clocked into the nRF2401A. The application protocol or MCU sets the speed <1Mbps (ex: 10kbps).
3. MCU sets CE low, this activates a nRF2401A ShockBurst�?transmission.
4. nRF2401A ShockBurst�?
�?RF front end is powered up
�?RF package is completed (preamble added, CRC calculated)
�?Data is transmitted at high speed (250 kbps or 1 Mbps configured by user).
�?nRF2401A return to stand-by when finished
nRF2401A in NO ShockBurstTM
nRF2401A Detects
Data content of registers:
PREAMBLE and
Incoming Data
ADDR PAYLOAD CRC
NO Correct
ADDR PAYLOAD CRC
nRF2401A Receives Data and
Checking CRC
ADDR PAYLOAD CRC
nRF2401A
Checks: Correct CRC?
ADDR PAYLOAD CRC
nRF2401A Set Data Ready (DR1/2) high
PAYLOAD
uController
Clocks out
Payload PAYLOAD
NO nRF2401A Register Empty?
nRF2401A Sets Data Ready (DR1/2) low
Output Register Empty
Figure 7 Flow Chart ShockBurst�?Receive of nRF2401A
nRF2401A ShockBurst�?Receive:
MCU interface pins: CE, DR1, CLK1 and DATA (one RX channel receive)
1. Correct address and size of payload of incoming RF packages are set when nRF2401A is configured to ShockBurst�?RX.
2. To activate RX, set CE high.
3. After 200 s settling, nRF2401A is monitoring the air for incoming communication.
4. When a valid package has been received (correct address and CRC found), nRF2401A removes the preamble, address and CRC bits.
5. nRF2401A then notifies (interrupts) the MCU by setting the DR1 pin high.
6. MCU may (or may not) set the CE low to disable the RF front end (low current mode).
7. The MCU will clock out just the payload data at a suitable rate (ex. 10 kbps).
8. When all payload data is retrieved nRF2401A sets DR1 low again, and is ready for new incoming data package if CE is kept high during data download. If the CE was set low, a new start up sequence can begin, see Figure 16.
Direct Mode
In direct mode the nRF2401A works like a traditional RF device. Data must be at
1Mbps ±200ppm, or 250kbps ±200ppm at low data rate setting, for the receiver to detect the signals.
Direct Mode Transmit:
MCU interface pins: CE, DATA
1. When application MCU has data to send, set CE high
2. The nRF2401A RF front end is now immediately activated, and after 200
s settling time, data will modulate the carrier directly.
3. All RF protocol parts must hence be implemented in MCU firmware
(preamble, address and CRC).
Direct Mode Receive:
MCU interface pins: CE, CLK1, and DATA
1. Once the nRF2401A is configured and powered up (CE high) in direct RX
mode, DATA will start to toggle due to noise present on the air.
2. CLK1 will also start to toggle as nRF2401A is trying to lock on to the incoming data stream.
3. Once a valid preamble arrives, CLK1 and DATA will lock on to the incoming signal and the RF package will appear at the DATA pin with the same speed as it is transmitted.
4. To enable the demodulator to re-generate the clock, the preamble must be
8 bits toggling hi-low, starting with low if the first data bit is low.
5. In this mode no data ready (DR) signals is available. Address and checksum verification must also be done in the receiving MCU.
DuoCeiver�?Simultaneous Two Channel Receive Mode
In both ShockBurst�?& direct modes the nRF2401A can facilitate simultaneous reception of two parallel independent frequency channels at the maximum data rate. This means:
�?nRF2401A can receive data from two 1 Mbps transmitters (ex: nRF2401A or nRF2402) 8 MHz (8 frequency channels) apart through one antenna interface.
�?The output from the two data channels is fed to two separate MCU
interfaces.
�?Data channel 1: CLK1, DATA, and DR1
�?Data channel 2: CLK2, DOUT2, and DR2
�?DR1 and DR2 are available only in ShockBurst�?
The nRF2401A DuoCeiver�?technology provides 2 separate dedicated data channels for RX and replaces the need for two, stand alone receiver systems.
nRF2401A Tx/Rx
nRF2401A Tx/Rx
nRF2401A Tx/Rx
Figure 8 Simultaneous 2 channel receive on nRF2401A
There is one absolute requirement for using the second data channel. For the nRF2401A to be able to receive at the second data channel the frequency channel must be 8MHz higher than the frequency of data channel 1. The nRF2401A must be programmed to receive at the frequency of data channel 1. No time multiplexing is used in nRF2401A to fulfil this function. In direct mode the MCU must be able to
handle two simultaneously incoming data packets if it is not multiplexing between the two data channels. In ShockBurst�?it is possible for the MCU to clock out one data channel at a time while data on the other data channel waits for MCU availability, without any lost data packets, and by doing so reduce the needed performance of the MCU.
FRF2=FRF1+8MHz
Clock Recovery, DataSlicer
Clock Recovery, DataSlicer
ADDR, CRC Check
ADDR, CRC Check
Data(FRF1)
Data(FRF2)
Figure 9 DuoCeiverTM with two simultaneously independent receive channels.
Configuration Mode
In configuration mode a configuration word of up to 15 bytes is downloaded to nRF2401A. This is done through a simple 3-wire interface (CS, CLK1 and DATA). For more information on configuration please refer to the nRF2401A Device configuration chapter on page16.
Stand-By Mode
Stand by mode is used to minimize average current consumption while maintaining short start up times. In this mode, part of the crystal oscillator is active. Current consumption is dependent on crystal frequency (Ex: 12 A @ 4 MHz, 32 A @ 16
MHz). The configuration word content is maintained during stand by.
Power Down Mode
In power down the nRF2401A is disabled with minimal current consumption, typically less than 1A. Entering this mode when the device is not active minimizes average current consumption, maximizing battery lifetime. The configuration word content is maintained during power down.
PRODUCT SPECIFICATION
nRF2401A Single Chip 2.4 GHz Radio Transceiver
Pin configuration for the different modes of nRF2401A
nRF2401A MODES
MODE SWITCHES INPUT PINS BIDIR PINS OUTPUT PINS
direction direction direction
RXMODE ShockBurst PWR_UP CE CS CLK1 DATA CLK2 DR1 DR2 DOUT2
In In In
Power down X X 0 1
1 X X X 0 0 0
In In In
Power down 0 1 0 X 0 X X X 0 0 0
In In In
Power down 1 1 0 X 0 CLK X X 0 0 0
In In In
Stand by 0 X 1 0 0 X X X 0 0 0
In In In
Stand by 1 0 1 0 0 X X X 0 0 0
In In2 In
Stand by 1 1 1 0 0 CLK DATA X 0 DR2 0
In Out3 In
Stand by 1 1 1 0 0 CLK DATA X 1 DR2 0
In In In
Configuration X X 1 0 1 CLK CONFIG DATA X 0 0 0
In In In
TX ShockBurst�?0 1 1 1 0 CLK DATA X 0 0 0
In In In
TX Direct 0 0 1 1 0 X DATA X 0 0 0
RX ShockBurst�?In Out In
in one channel 1 1 1 1 0 CLK DATA X DR1 0 0
RX ShockBurst�?In Out In
in two channels 1 1 1 1 0 CLK DATA CLK DR1 DR2 DATA
RX Direct
Out Out Out
in one channel 1 0 1 1 0 CLK DATA 0 0 0 0
RX Direct
Out Out Out
in two channels 1 0 1 1 0 CLK DATA CLK 0 0 DATA
Table 7 Pin configuration of nRF2401A.
1 In = X means the input should be set to either “low�?or “high�?
2 Input if DR1 is “low�?
3 Output if DR1 is “high�?Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Revision: 1.0 Page 15 of 38 December 2004
DEVICE CONFIGURATION
All configuration of the nRF2401A is done via a 3-wire interface to a single configuration register. The configuration word can be up to 15 bytes long for ShockBurst�?use and up to 2 bytes long for direct mode.
Configuration for ShockBurst�?operation
The configuration word in ShockBurst�?enables the nRF2401A to handle the RF protocol. Once the protocol is completed and loaded into nRF2401A only one byte, bit[7:0], needs to be updated during actual operation.
The configuration blocks dedicated to ShockBurst�?is as follows:
�?Payload section width: Specifies the number of payload bits in a RF package.
This enables the nRF2401A to distinguish between payload data and the CRC
bytes in a received package.
�?Address width: Sets the number of bits used for address in the RF package.
This enables the nRF2401A to distinguish between address and payload data.
�?Address (RX Channel 1 and 2): Destination address for received data.
�?CRC: Enables nRF2401A on-chip CRC generation and de-coding.
These configuration blocks, with the exception of the CRC, are dedicated for the packages that a nRF2401A is to receive.
In TX mode, the MCU must generate an address and a payload section that fits the configuration of the nRF2401A that is to receive the data.
When using the nRF2401A on-chip CRC feature ensure that CRC is enabled and uses the same length for both the TX and RX devices.
PRE-AMBLE ADDRESS PAYLOAD CRC
Figure 10 Data packet set-up
Configuration for Direct Mode operation
For direct mode operation only the two first bytes (bit[15:0]) of the configuring word
are relevant.
Configuration Word overview
Bit position
Number of bits
Name Function
143:120 24 TEST Reserved for testing
119:112 8 DATA2_W Length of data payload section RX channel 2
111:104 8 DATA1_W Length of data payload section RX channel 1
103:64 40 ADDR2 Up to 5 byte address for RX channel 2
63:24 40 ADDR1 Up to 5 byte address for RX channel 1
23:18 6 ADDR_W Number of address bits (both RX channels).
17 1 CRC_L 8 or 16 bit CRC
16 1 CRC_EN Enable on-chip CRC generation/checking.
15 1 RX2_EN Enable two channel receive mode
14 1 CM Communication mode (Direct or ShockBurst�?
13 1 RFDR_SB RF data rate (1Mbps requires 16MHz crystal)
12:10 3 XO_F Crystal frequency
9:8 2 RF_PWR RF output power
7:1 7 RF_CH# Frequency channel
0 1 RXEN RX or TX operation
Table 8 Table of configuration words.
The configuration word is shifted in MSB first on positive CLK1 edges. New configuration is enabled on the falling edge of CS.
On the falling edge of CS, the nRF2401A updates the number of bits actually shifted in during the last configuration.
If the nRF2401A is to be configured for 2 channel RX in ShockBurst�? a total of 120 bits must be shifted in during the first configuration after VDD is applied.
Once the wanted protocol, modus and RF channel are set, only one bit (RXEN) is shifted in to switch between RX and TX.
Configuration Word Detailed Description
The following describes the function of the 144 bits (bit 143 = MSB) that is used to configure the nRF2401A.
General Device Configuration: bit[15:0] ShockBurst�?Configuration: bit[119:16] Test Configuration: bit[143:120]
MSB TEST
D143 D142 D141 D140 D139 D138 D137 D136
Reserved for testing
1 0 0 0 1 1 1 0 Default
MSB TEST
D135 D134 D133 D132 D131 D130 D129 D128 D127 D126 D125 D124 D123 D122 D121 D120
Reserved for testing Close PLL in TX
0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 Default
DATA2_W
D119 D118 D117 D116 D115 D114 D113 D112
Data width channel#2 in # of bits excluding addr/crc
0 0 1 0 0 0 0 0 Default
DATA1_W
D111 D110 D109 D108 D107 D106 D105 D104
Data width channel#1 in # of bits excluding addr/crc
0 0 1 0 0 0 0 0 Default
D103 D102 D101 �? D71 D70 D69 D68 D67 D66 D65 D64
Channel#2 Address RX (up to 40bit)
0 0 0 �?1 1 1 0 0 1 1 1 Default
D63 D62 D61 �? D31 D30 D29 D28 D27 D26 D25 D24
Channel#1 Address RX (up to 40bit)
0 0 0 �?1 1 1 0 0 1 1 1 Default
D23 D22 D21 D20 D19 D18
Address width in # of bits (both channels)
0 0 1 0 0 0 Default
D17 D16
CRC Mode 1 = 16bit, 0 = 8bit CRC 1 = enable; 0 = disable
0 1 Default
RF-Programming LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Two Ch. BUF OD XO Frequency RF Power Channel selection RXEN
0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 Default
Table 9 Configuration data word
The MSB bit should be loaded first into the configuration register.
Default configuration word: h8E08.1C20.2000.0000.00E7.0000.0000.E721.0F04.
ShockBurst�?configuration:
The section bit[119:16] contains the segments of the configuration register dedicated
to ShockBurst�?operational protocol. After VDD is turned on ShockBurst�?configuration is done once and remains set whilst VDD is present. During operation only the first byte for frequency channel and RX/TX switching need to be changed.
PLL_CTRL
Bit 121-120:
PLL_CTRL
D121 D120 PLL
0 0 Open TX/Closed RX
0 1 Open TX/Open RX
1 0 Closed TX/Closed RX
1 1 Closed TX/Open RX
Table 10 PLL setting.
PLL_CTRL: Controls the setting of the PLL for test purposes. With closed PLL in TX no deviation will be present. For normal operational mode these two bits must both be low.
DATAx_W
DATA2_W
119 118 117 116 115 114 113 112
Bit 119 �?112:
DATA1_W
111 110 109 108 107 106 105 104
Table 11 Number of bits in payload.
DATA2_W: Length of RF package payload section for receive-channel 2.
Bit 111 �?104:
DATA1_W: Length of RF package payload section for receive-channel 1.
The total number of bits in a ShockBurst�?RF package may not exceed 256! Maximum length of payload section is hence given by:
DATAx _ W (bits) �?256 �?ADDR _ W �?CRC
ADDR_W: length of RX address set in configuration word B[23:18] CRC: check sum, 8 or 16 bits set in configuration word B[17]
PRE: preamble, 8 bits are automatically included
Shorter address and CRC leaves more room for payload data in each package.
103 102 101 �? 71 70 69 68 67 66 65 64
63 62 61 �? 31 30 29 28 27 26 25 24
Table 12 Address of receiver #2 and receiver #1.
Bit 103 �?64:
ADDR2: Receiver address channel 2, up to 40 bit.
Bit 63 �?24: ADDR1
ADDR1: Receiver address channel 1, up to 40 bit.
Bits in ADDRx exceeding the address width set in ADDR_W are redundant and can be set to logic 0.
ADDR_W & CRC
ADDR_W CRC_L CRC_EN
23 22 21 20 19 18 17 16
Table 13 Number of bits reserved for RX address + CRC setting.
Bit 23 �?18:
ADDR_W: Number of bits reserved for RX address in ShockBurst�?packages.
Maximum number of address bits is 40 (5 bytes). Values over 40 in
ADDR_W are not valid.
Bit 17:
CRC_L: CRC length to be calculated by nRF2401A in ShockBurst�?
Logic 0: 8 bit CRC Logic 1: 16 bit CRC
Bit: 16:
CRC_EN: Enables on-chip CRC generation (TX) and verification (RX).
Logic 0: On-chip CRC generation/checking disabled
Logic 1: On-chip CRC generation/checking enabled
An 8 bit CRC will increase the number of payload bits possible in each
ShockBurst�?data packet, but will also reduce the system integrity.
General device configuration:
This section of the configuration word handles RF and device related parameters. Modes:
RX2_EN CM RFDR_SB XO_F RF_PWR
15 14 13 12 11 10 9 8
Table 14 RF operational settings.
Bit 15:
RX2_EN:
Logic 0: One channel receive
Logic 1: Two channels receive
In two channels receive, the nRF2401A receives on two, separate frequency channels simultaneously. The frequency of receive channel
1 is set in the configuration word bit[7-1], receive channel 2 is always
8 channels (8 MHz) above receive channel 1.
Bit 14:
Communication Mode:
Logic 0: nRF2401A operates in direct mode.
Logic 1: nRF2401A operates in ShockBurst�?mode
Bit 13:
RF Data Rate:
Logic 0: 250 kbps
Logic 1: 1 Mbps
Utilizing 250 kbps instead of 1Mbps will improve the receiver sensitivity by 10 dB. 1Mbps requires 16MHz crystal.
Bit 12-10:
XO_F: Selects the nRF2401A crystal frequency to be used:
XO FREQUENCY SELECTION
D12 D11 D10 Crystal Frequency [MHz]
0 0 0 4
0 0 1 8
0 1 0 12
0 1 1 16
1 0 0 20
Table 15 Crystal frequency setting.
Bit 9-8:
RF_PWR: Sets nRF2401A RF output power in transmit mode:
RF OUTPUT POWER
D9 D8 P [dBm]
0 0 -20
0 1 -10
Table 16 RF output power setting.
RF channel & direction
RF_CH# RXEN
7 6 5 4 3 2 1 0
Table 17 Frequency channel and RX / TX setting.
Bit 7 �?1:
RF_CH#: Sets the frequency channel the nRF2401A operates on.
The channel frequency in transmit is given by:
ChannelRF �?2400 MHz �?RF _ CH # �?1.0 MHz
RF_CH #: between 2400MHz and 2527MHz may be set.
The channel frequency in data channel 1 is given by:
ChannelRF �?2400 MHz �?RF _ CH # �?1.0 MHz
(Receive at PIN#8)
RF_CH #: between 2400MHz and 2524MHz may be set.
The channels above 83 can only be utilized in certain territories (ex: Japan)
The channel frequency in data channel 2 is given by:
ChannelRF �?2400 MHz �?RF _ CH # �?1.0 MHz +8MHz (Receive at PIN#4)
RF_CH #: between 2408MHz and 2524MHz may be set.
Set active mode:
Logic 0: transmit mode
Logic 1: receive mode
DATA PACKAGE DESCRIPTION
PRE-AMBLE ADDRESS PAYLOAD CRC
Figure 11 Data Package Diagram
The data packet for both ShockBurst�?mode and direct mode communication is divided into 4 sections. These are:
1. PREAMBLE �?The preamble field is required in ShockBurst�?and Direct modes.
�?Preamble is 8 bits in length and is dependent of the first data bit in direct
PREAMBLE 1st ADDR-BIT
01010101 0
10101010 1
�? Preamble is automatically added to the data packet in ShockBurst�?and thereby gives extra space for payload. In Direct mode MCU must handle preamble.
In ShockBurst�?mode RX, the preamble is removed from the received output data, in direct mode the preamble is transparent to the output data.
2 ADDRESS �?The address field is required in ShockBurst�?mode.1
�?8 to 40 bits length.
�?Address automatically removed from received packet in ShockBurst�?mode. In Direct mode MCU must handle address.
3 PAYLOAD �?The data to be transmitted
�?In ShockBurst�?mode payload size is 256 bits minus the following:
(Address: 8 to 40 bits. + CRC 8 or 16 bits).
�?In Direct mode the maximum packet size (length) is for 1Mbps 4000 bits
4 CRC �?The CRC is optional in ShockBurst�?mode, and is not used in Direct mode.
�?8 or 16 bits length
�?The CRC is removed from the received output data in ShockBurst�?RX.
Table 18 Data package description
1 Suggestions for the use of addresses in ShockBurst�? In general more bits in the address gives less false detection, which in the end may give lower data packet loss.
A. The address made by (5, 4, 3, or 2) equal bytes are not recommended because it in general will make the packet-error-rate increase.
B. Addresses where the level shift only one time (i.e. 000FFFFFFF) could often be detected in noise that may give a false detection, which again may give raised packet-error-rate.
Direct mode will be dependent on the software used in the MCU, but it is recommended to have the same restrictions on addresses for this mode.
IMPORTANT TIMING DATA
The following timing applies for operation of nRF2401A.
nRF2401A Timing Information
nRF2401A timing Max. Min. Name PWR_DWN Î Configuration mode 3ms Tpd2cfgm PWR_DWNÎ Active mode (RX/TX) 3ms Tpd2a
ST_BY Î TX ShockBurst�?195s Tsby2txSB ST_BY Î TX Direct Mode 202s Tsby2txDM ST_BY Î RX mode 202s Tsby2rx Minimum delay from CS to data. 5s Tcs2data Minimum delay from CE to data. 5s Tce2data Minimum delay from DR1/2 to clk. 50ns Tdr2clk Maximum delay from clk to data. 50ns Tclk2data Delay between edges 50ns Td
Setup time 500ns Ts Hold time 500ns Th Delay to finish internal GFSK data 1/data rate Tfd Minimum input clock high 500ns Thmin Set-up of data in Direct Mode 50ns Tsdm Minimum clock high in Direct Mode 300ns Thdm Minimum clock low in Direct Mode 230ns Tldm Time on air, TX Direct mode 4ms ToaDM
Table 19 Operational timing of nRF2401A
When the nRF2401A is in power down it must always settle in stand by for 3ms before it can enter configuration or one of the active modes.
Tpd2cfgm
Figure 12 Timing diagram for power down (or VDD off) to configuration mode for nRF2401A.
Figure 13 Power down (or VDD off) to active mode
Note that the configuration word will be lost when VDD is turned off and that the device then must be configured before going to one of the active modes. If the device is configured one can go directly from power down to the wanted active mode.
CE and CS may not be high at the same time. Setting one or the other decides whether configuration or active mode is entered.
Configuration mode timing
When one or more of the bits in the configuration word needs to be changed the following timing apply.
CE CLK1
Figure 14 Timing diagram for configuration of nRF2401A
If configuration mode is entered from power down, CS can be set high after Tpd2sby as shown in Figure 12.
ShockBurst�?Mode timing
ShockBurst�?TX:
ANT1/ANT2 .
Td Tsby2txSB Toa
CE CLK1
Figure 15 Timing of ShockBurst�?in TX
The package length and the data rate give the delay Toa (time on air), as shown in the equation.
TOA �?1/ datarate �?(# databits �?1)
ShockBurst�?RX:
DATA/DOUT2
ANT1/ANT2 .
Td Tsby2rx
Figure 16 Timing of ShockBurst�?in RX
The CE may be kept high during downloading of data, but the cost is higher current consumption (18mA) and the benefit is short start-up time (200s) when DR1 goes low.
Direct Mode
Direct Mode TX:
ANT1/ANT2
Td Tsby2txDM ToaDM Tfd
Figure 17 Timing of direct mode TX
In TX direct mode the input data will be sampled by nRF2401A and therefore no clock is needed. The clock must be stable at low level during transmission due to noise considerations. The exact delay Tsby2txDM is given by the equation:
Tsby 2txDM
�?194us �?1/ FXO �?14 �?2.25us
The maximum length of a package (ToaDM) over all voltages and temperatures is
4ms. This is limited by frequency drift in the transmitter and is independent of data rate and frequency channel.
Direct Mode RX:
DATA/DOUT2
ANT1/ANT2
Td Tsby2rx
CE Thdm Tldm
DATA/DOUT2
Figure 18 Timing of direct mode RX
Tsby2rx describes the delay from the positive edge of CE to start detection of
(demodulating) incoming data.
PERIPHERAL RF INFORMATION
Antenna output
The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD, either via a RF choke or via the center point in a dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be in the range 200-700�? A load of 100�?j175�?is recommended for maximum output power (0dBm). Lower load impedance (for instance 50 �? can be obtained by fitting a simple matching network.
Output Power adjustment
Power setting bits of configuring word
RF output power DC current consumption
11 0 dBm ±3dB 13.0 mA
10 -5 dBm ±3dB 10.5 mA
01 -10 dBm ±3dB 9.4 mA
00 -20 dBm ±3dB 8.8 mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 100�?j175�?
Table 20 RF output power setting for the nRF2401A.
Crystal Specification
Tolerance includes initially accuracy and tolerance over temperature and aging.
Frequency CL ESR C0max Tolerance
4 12pF 150 �?7.0pF ±30ppm
8 12pF 100 �?7.0pF ±30ppm
12 12pF 100 �?7.0pF ±30ppm
16 12pF �?�?7.0pF ±30ppm
20 12pF �?�?7.0pF ±30ppm
Table 21 Crystal specification of the nRF2401A
To achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. Specifying CL=12pF is OK, but it is possible to use up to 16pF. Specifying a lower value of crystal parallel equivalent capacitance, C0 will also work, but this can increase the price of the crystal itself. Typically C0=1.5pF at a crystal specified for C0max=7.0pF.
Sharing crystal with micro controller.
When using a micro controller to drive the crystal reference input XC1 of the nRF2401A transceiver some rules must be followed.
Crystal parameters:
When the micro controller drives the nRF2401A clock input, the requirement of load capacitance CL is set by the micro controller only. The frequency accuracy of 30 ppm is still required to get a functional radio link. The nRF2401A will load the crystal by
0.5pF at XC1 in addition to the PBC routing.
Input crystal amplitude & Current consumption
The input signal should not have amplitudes exceeding any rail voltage, but any DC- voltage within this is OK. Exceeding rail voltage will excite the ESD structure and the radio performance is degraded below specification. If testing the nRF2401A with a
RF source with no DC offset as the reference source, the input signal will go below the ground level, which is not acceptable.
Buffer: Sine to full swing
Amplitude controlled current source
Current starved inverter: XOSC core
Figure 19 Principle of crystal oscillator
It is recommended to use a DC-block before the XC1 pin so that the internal ESD
structures will self bias the XC1 voltage .
The nRF2401A crystal oscillator is amplitude regulated. To achieve low current consumption and also good signal-to-noise ratio, it is recommended to use an input signal larger than 0.4 V-peak. The needed input swing is independent of the crystal
frequency. When clocking the nRF2401A externally, XC2 is not used and can be left as an open pin.
Frequency Reference MCU
In direct mode there is a requirement on the accuracy of the data rate. For the receiver
to detect the incoming data and recover the clock, the data rate must be within
±200ppm, given that the data is "random", i.e. there is a statistical calculation on how often a preamble like sequence is present in the data. The clock is synchronized for any preamble detection, be it a dedicated preamble or part of the data stream.
PCB layout and de-coupling guidelines
A well-designed PCB is necessary to achieve good RF performance. Keep in mind
that a poor layout may lead to loss of performance, or even functionality, if due care is not taken. A fully qualified RF-layout for the nRF2401A and its surrounding components, including matching networks, can be downloaded from.
A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The nRF2401A DC supply voltage should be de-coupled as close as possible to the VDD pins with high performance RF capacitors, see Table 22. It is preferable to mount a large surface mount capacitor (e.g. 4.7F tantalum) in parallel with the smaller value capacitors. The nRF2401A supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the nRF2401A IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. One via hole should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the crystal or the power supply lines.
APPLICATION EXAMPLE
nRF2401A with single ended matching network
PWR_UP CE DR2
1 CE
2 DR2
3 CLK2
4 DOUT2
5 CS
6 DR1
nRF2401
VSS 18
VDD 17
VSS_PA 16
ANT2 15
ANT1 14
VDD_PA 13
C4 C3
5.6nH C10
U1 nRF2401
QFN24/5X5
16 MHz
Figure 20 nRF2401A schematic for RF layouts with single end 50�?antenna
Component Description Size Value Toleranc e
C1 Capacitor ceramic, 50V, NPO 0603 22 ±5% pF C2 Capacitor ceramic, 50V, NPO 0603 22 ±5% pF C3 Capacitor ceramic, 50V, NPO 0603 4.7 ±5% pF C4 Capacitor ceramic, 50V, X7R 0603 2.2 ±10% nF C5 Capacitor ceramic, 50V, X7R 0603 1.0 ±10% nF C6 Capacitor ceramic, 50V, X7R 0603 10 ±10% nF C7 Capacitor ceramic, 50V, X7R 0603 33 ±10% nF R1 Resistor 0603 1.0 ±1% M�?R2 Resistor 0603 22 ±1% k�?U1 nRF2401A transceiver QFN24 / 5x5 nRF2401A
X1 Crystal, CL = 12pF, ESR < 100 ohm
LxWxH =
4.0x2.5x0.8
161) +/- 30 ppm MHz
L1 Inductor, wire wound 2) 0603 3.3 ± 5% nH L2 Inductor, wire wound 2) 0603 10 ± 5% nH
L3 Inductor, wire wound 2) 0603 5.6 ± 5% nH L4 Inductor, wire wound 2) 0603 5.6 ± 5% nH
C8 Ceramic capacitor, 50V, NP0 0603 1.0 ± 0.1 pF pF C9 Ceramic capacitor, 50V, NP0 0603 1.0 ± 0.1 pF pF C10 Ceramic capacitor, 50V, NP0 0603 2.2 ± 0.25 pF pF C11 Ceramic capacitor, 50V, NP0 0603 4.7 ± 0.25 pF pF
Table 22 Recommended components (BOM) in nRF2401A with antenna matching network
1) nRF2401A can operate at several crystal frequencies, please refer to page 31.
2) Wire wound inductors are recommended, other can be used if their self-resonant frequency (SFR) is
> 2.7 GHz
PCB layout example
Figure 21 shows a PCB layout example for the application schematic in Figure 20.
A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane.
Top silk screen
No components in bottom layer
Top view Bottom view
Figure 21 nRF2401A RF layout with single ended connection to 50�?antenna and
0603 size passive components
DEFINITIONS
Data sheet status
Objective product specification This data sheet contains target specifications for product development.
Preliminary product specification
This data sheet contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later.
Product specification This data sheet contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 23. Definitions
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale.
Product Specification: Revision Date: 23.12.2004.
Data sheet order code: 231204-nRF2401A or 231204-nRF2401AG
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
YOUR NOTES
Nordic Semiconductor ASA �?World Wide Distributors
For Your nearest dealer, please see
Main Office:
Vestre Rosten 81, N-7075 Tiller, Norway
Phone: +47 72 89 89 00, Fax: +47 72 89 89 89
Visit the Nordic Semiconductor ASA website at

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TDA3651A TDA3651AQ
VERTICAL DEFLECTION CIRCUIT (900)
The TDA3651 is a vertical deflection output circuit for drive of various deflection systems with deflection currents up to 1,5 A peak-to-peak.
The circuit incorporates the following functions:
�?Driver
�?Output stage
�?Thermal protection and output stage protection
�?Flyback generator
�?Voltage stabilizer
QUICK REFERENCE DATA
Supply voltage (pin 9) = Vp 0 to 50 V Peak output voltage during flyback (pin 5) V54M < 55 V Output current (peak-to-peak value) 15(p-p) < 1,5 A Operating junction temperature T max. 150 O
VOLTAGE PLY8ACK. 8
7 STABILIZER TDA3651 GENERATOR
I CURRENT
T SOURCE
deflection to
3 leedEicE
PROTEC11ON PROTECTION
1 DRIVER
2 7188390.
Fig. 1 Block diagram.
PACKAGE OUTLINES
TDA3651: 9-lead SIL; plastic (SOT-i lOB). TDA3651A: 9-lead SIL; plastic power (SOT- 131).
TDA3651AO: 9-lead SI L bent to DI L; plastic power (SOT- 157).
GENERAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4. The output transistors of the class-B output stage can each deliver 0,75 A maximum. The ‘upper�?power transistor is protected against short-circuit currents to ground, whereas, during flyback, the ‘lower�?power transistor is protected against too high voltages which may occur during adjustments.
Moreover, the output transistors have been given extra solidity by means of special measures in the
internal circuit layout.
A thermal protection circuit is incorporated to protect the IC against too high dissipation. This circuit
is ‘active�? at 175 °C and then reduces the deflection current to such a value that the dissipation cannot
increase.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via a resistor to pin 3 which is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage and so limits the turn-off dissipation. It also allows a quick start of the flyback generator. Pin 3 is connected externally via resistors to pin 1 in order to allow for different applications in which pin 3 and pin 1 are driven separately.
Flyhack generator
The capacitor at pin 6 is charged to a maximum voltage, which is equal to the supply voltage Vp (pin 9), during scan.
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage (pin 9),
the flyback generator is activated. The Vp is connected in series (via pin 8) with the voltage across the capacitor.
The voltage at the supply pin (pin 6) of the output stage will then be maximum twice Vp. Lower voltages can be chosen by changing the value of the external resistor at pin 8.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V for drive of the output stage, so the drive current of the output stage is not affected by supply voltage variations. The stabilized voltage is available at pin 7.
A decoupling capacitor of 2,2 j.tF can be connected to this pin.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages (pins 4 and 2 externally connected to ground)
Output voltage (pin 5) V54 max. 55 V Supply voltage (pin 9) V94 = Vp max. 50 V Supply voltage output stage (pin 6) V64 max. 55 V Input voltage (pins 1 and 3) V12 V32 max. Vp
Currents
Repetitive peak output current (pin 5) ± 1SRM max. 0,75 A Non-repetitive peak output current (pin 5) ± 155M max. 1,5 A*
Repetitive peak flyback generator �? 75 A
output current (pin 8) 18RM max. +085 A
Non-repetitive peak flyback generator �? 5 A
output current (pin 8) 18SM max. + A*
Temperatures
Storage temperature range Tstg �?5 to + 150 °C Operating ambient temperature range Tamb �?5 to + 65 °C Operating junction temperature range T �?5 to + 150 °C
CHARACTER ISTICS
Tamb = 25 °C; Vp = 26 V; pins 4 and 2 externally connected to ground; unless otherwise specified.
Outputcurrent (peak-to-peak value) 15p-p
Flyback generator output current —l
Flyback generator output current 18
typ. 12A
typ. 07 A
< 045 A
typ. 06 A
< 0,75 A
Output voltages
Peak voltage during flyback V54M < 55 V
Saturation voltage to supply at —l = 0,75 A —Vsst
Saturation voltage to ground at l
=0,75 A
typ. 25V V54wt < 30 V
Saturation voltage to supply at —I = 0,6 A —Vst WP- 2,2 V
typ. 2,2 V
Saturation voltage to ground at l
0=,6 A V54t
Non-repetitive duty factor maximum 3,3%.
Supply voltage
Supply voltage output stage
Supply current (no load and no quiescent current)
Quiescent current (see Fig. 2)
Variation of quiescent current with temperature
10 to 50
25 to 52
Flyback generator
Saturation voltage at �?8 = 0,85 A Saturation voltage at 18 = 0,75 A Saturation voltage at 18 = 0,7 A
Saturation voltage at 18 = 0,6 A Flyback generator active if:
Leakage current
Input current for ± 15 = 0,75 A Input voltage during scan
Input current during scan Input voltage during scan Input voltage during flyback
typ. 1,6 V
typ. 2,5 V
< 3,OV
typ. 1,4 V
< l,9V
typ. 2,3 V
< 2,8V
typ. 5 pA
< lOOpA
typ. 230 pA
175 to 380 pA
typ. 1,9 V
0,9to2,7 V
0,01 to 2,5 mA
0,9toVp V OtoO,2 V
Voltage at pin 7
Load current of pin 7
Unloaded voltage at pin 7 during flyback
Junction temperature of
typ. typ.
5,6to6,9 V
switching on the thermal protection
158 to 192 °C
Thermal resistance from crystal to mounting base
TDA3651
typ. Rth c-mb <
TDA3651A; AQ
Rth c-tab
10 K/W
12 K/W
Power dissipation
Open loop gain at 1 kHz; Rload = 1 kZ Frequency response (�? dB); Rload = 1 k2
see Fig. 3a or 3b
G0 typ. f typ.
Take care that during flyback the voltage at pin 5 does not exceed 55 V.
7Z 883 89
0 25 Vp(V) 50
Fig. 2 Quiescent current 14 as a function of supply voltage Vp.
(W) infinite heatsjnk
7Z88387 1
no heatonk
65 100 Tamb(°CI 150
Fig. 3a Power derating curves TDA3651.
20 7Z 883 88
HHIIII I
“tot f I infinite heatsink
(WI Rthh.a=
no heatsink
0 50 100 Tb(°C) 150
Fig. 3b Power derating curves TDA3651A; AQ.
APPLICATION INFORMATION
The following application data are measured in a typical application as shown in Figs 4 and 5. Deflection current (including 6% overscan)
peak-to-peak value �?(pp) typ.
Supply voltage vg4 typ. Total supply current typ.
Peak output voltage during flyback V54M <
Saturation voltage to supply
Saturation voltage to ground
Flyback time
Total power dissipation in IC Operating ambient temperature
typ. 2,0 V V56sat < 2,5 V
typ. 2,0 V VS4sat < 2,5 V
typ. 0,95 ms tfl < 1,2 ms
‘tot typ. 2,5 W Tamb < 65 °C
TDA3651
2 4 5 6
6.8 k&2
VERTICAL
vertical drive
I from pin 1 TDA2578A)
vertical 12 k
1OOnF DEFLECTION COILS
AT1236/20
10 kS2 22OiF
1pm 3
TDA2578A) i
feedback
lpin2 1,8nF I
+ 15OOF
TDA2578A1
7Z86169.A
I a. 1OO
amplitude
Fig. 4 Typical application circuit diagram of the TDA3651 (vertical output), when used in combina­
tion with the TDA2578A (see Fig. 5).
Note to deflection coils AT1236/20: L = 29 mH, R = 13,6 2; deflection current without overscan is
0,82 A peak-to-peak and EHT voltage is 25 kV.
horizontal
horizontal
flyback sandcastle pulse
+12V drive
>0,2 mA
mute L.
- I ++
lkfl 6,8 36k2 220
kfZ jsF nF
10 11 12 13 14 15 16 17 18
T0A2578A
9 8 7 6 5 4 3 2 1
4,7 ktZ
1 100 kU kQ
 �?150 + 22 + 1 150 ÷ 680
nF jzF isF PF;
pF nF
56k12 220_
to ad). (horizontal) vertical vertical
(vertical)
feedback drive
video + from pin 9
TDA3651 lzselee.A
Fig. 5 Typical application circuit diagram; for combination of the TDA2578A with the TDA3651 (see Fig. 4).
I I +J\I
33k1Z topin lpF
�?2V 18
leoktz TDA257SA
14 .—CJ )�?. 47kc2 220k12
TDA2S7SA
/ lZS6tOO
i ) a
�?)zae3lt
Fig. 6 Circuit configuration at pin 14 for Fig. 7 Circuit configuration at pin-18 for phase adjustment. VCR mode.
1 kS2 resistor between pin 18 and + 12 V:
without mute function.
220 kS2 between pin 18 and ground:
with mute function.
TDA36S1AQ
TDA36S1
9 8 7 6 5 4 3 2
47f)i+220
+265 r
DEFLECTION
CCII 470(1
AT 1239
..,._10060F
200k11
uideo input
‘tt t . 1D
(GOnE 4 70F 220F I oF I5OpF..,... 220611
1.56(1 22(1 56
hill i LA
IlSOnF 4.7nF�?611 651
8 7 6 5 4 3 2 1
TOA2579
tO 11 12 13 14 15 16 17 18
hotizontal I 68611 1 1 sandoastle
1 1 transmission
I I idenslication
02(03 OmA 100 33 10 J_. +
50/60HZ
identiliuation
£22F 100nF
+120 honi200tal
476(1 476(1
horizontal In ad
>6,2 mA
7Z8 1402
Ilyback unllage
Fig. 8 Application circuit diagram for combination of TDA3651 with TDA2579.

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Meets or Exceeds the Requirements of TIA/EIA-422-B and ITU Recommendation V.11
Low Power, ICC = 100 A Typ
AM26C31M ...J OR W PACKAGE AM26C31Q ...D PACKAGE
AM26C31C . . . D, DB, N, OR NS PACKAGE
AM26C31I . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
High Speed, tPLH = tPHL = 7 ns Typ
Low Pulse Distortion, tsk(p) = 0.5 ns Typ
High Output Impedance in Power-Off
Conditions
�? High-Reliability Automotive Applications
�? Configuration Control/Print Support
�? Qualification to Automotive Standards
description/ordering information
The AM26C31 is a differential line driver with complementary outputs, designed to meet the
AM26C31M . . . FK PACKAGE (TOP VIEW)
3 2 1 20 19
requirements of TIA/EIA -422-B and ITU (formerly CCITT). The 3-state outputs have high-current capability for driving balanced lines, such as twisted-pair or parallel-wire transmission lines,
and they provide the high-impedance state in the power-off condition. The enable functions are common to all four drivers and offer the choice of an active-high (G) or active-low (G) enable input. BiCMOS circuitry reduces power consumption without sacrificing speed.
2Y 8 14 3Z
9 10 11 12 13
NC �?No internal connection
The AM26C31C is characterized for operation from 0C to 70C, the AM26C31I is characterized for operation from �?0C to 85C, the AM26C31Q is characterized for operation over the automotive temperature range of
�?0C to 125C, and the AM26C31M is characterized for operation over the full military temperature range of
�?5C to 125C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
 ! " #$ % !&
% "! "! '! ! !( !
% % ) *& % " ! + % ! ! ! $* $ %!
Copyright �?2004, Texas Instruments Incorporated
" % "$ , , -. ./ $$ " ! ! ! ! !%
$! '! ) ! !%& $$ '! " % / " %
description/ordering information (continued)
ORDERING INFORMATION
PACKAGE�?ORDERABLE PART NUMBER
TOP-SIDE MARKING
0C to 70C
PDIP (N)
Tube of 25
AM26C31CN
AM26C31CN
SOIC (D)
Tube of 40
AM26C31CD
AM26C31C
Reel of 2500
AM26C31CDR
SOP (NS)
Reel of 2000
AM26C31CNSR
SSOP (DB)
Reel of 2000
AM26C31CDBR
�?0C to 85C
PDIP (N)
Tube of 25
AM26C31IN
AM26C31IN
SOIC (D)
Tube of 40
AM26C31ID
AM26C31C
Reel of 2500
AM26C31IDR
SOP (NS)
Reel of 2000
AM26C31INSR
SSOP (DB)
Reel of 2000
AM26C31IDBR
TSSOP (PW)
Tube of 90
AM26C31IPW
26C31I
�?0C to 125C
SOIC (D)
Tube of 40
AM26C31QD
AM26C31QD
Reel of 2500
AM26C31QDR
�?5C to 125C
CDIP (J)
Tube of 25
AM26C31MJ
AM26C31MJ
CFP (W)
Tube of 150
AM26C31MW
AM26C31MW
LCCC (FK)
Tube of 55
AM26C31MFK
AM26C31MFK
�?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at.
FUNCTION TABLE (each driver)
INPUT A
ENABLES
OUTPUTS
H L H L
H X H X X L X L
L H
H L L H H L L H
Z Z
H = High level, L = Low level, X = Irrelevant, Z = High impedance (off)
logic diagram (positive logic)
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Output
GND GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)�?Supply voltage range, VCC (see Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
�?.5 V to 7 V
Input voltage range, VI
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . �?.5 V to VCC + 0.5 V
Differential input voltage range, VID
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . �?4 V to 14 V
Output voltage range, VO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
�?.5 V to 7 V
Input or output clamp current, IIK or IOK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
�?0 mA
Output current, IO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . �?50 mA
VCC current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
200 mA
GND current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . �?00 mA
Package thermal impedance, JA (see Notes 2 and 3): D package DB package N package NS package
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
73C/W
PW package
. . . . . . . . . . . . . . . . . . . . . . . . . 108C/W
Operating virtual junction temperature, TJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . �?5C to 150C
�?Stresses beyond those listed under “absolute maximum ratings�?may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions�?is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential output voltage (VOD), are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) �?TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM MAX
VCC Supply voltage
4.5 5 5.5
VID Differential input voltage
VIH High-level input voltage
VIL Low-level input voltage
IOH High-level output current
IOL Low-level output current
TA Operating free-air temperature
AM26C31C
AM26C31I
�?0 85
AM26C31Q
�?0 125
AM26C31M
�?5 125
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AM26C31C AM26C31I
MIN TYP�?MAX
VOH High-level output voltage
IO = �?0 mA
2.4 3.4
VOL Low-level output voltage
IO = 20 mA
0.2 0.4
|VOD| Differential output voltage magnitude
RL = 100 Ω�?See Figure 1
∆|VOD| Change in magnitude of differential output voltage�?RL = 100 Ω�?See Figure 1
VOC Common-mode output voltage
RL = 100 Ω�?See Figure 1
∆|VOC| Change in magnitude of common-mode output voltage�?RL = 100 Ω�?See Figure 1
II Input current
VI = VCC or GND
IO(off) Driver output current with power off
VCC = 0
VO = 6 V
VO = �?.25 V
IOS Driver output short-circuit current
VO = 0
�?0 �?50
IOZ High-impedance off-state output current
VO = 2.5 V
VO = 0.5 V
ICC Quiescent supply current
VI = 0 V or 5 V
VI = 2.4 V or 0.5 V, See Note 4
Ci Input capacitance
�?All typical values are at VCC = 5 V and TA = 25C.
�?|VOD| and |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
NOTE 4: This parameter is measured per input. All other inputs are at 0 or 5 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AM26C31C AM26C31I
MIN TYP�?MAX
tPLH Propagation delay time, low- to high-level output
S1 is open, See Figure 2
3 7 12
tPHL Propagation delay time, high- to low-level output
S1 is open, See Figure 2
3 7 12
tsk(p) Pulse skew time (|tPLH �?tPHL|)
S1 is open, See Figure 2
tr(OD), tf(OD) Differential output rise and fall times
S1 is open, See Figure 3
tPZH Output enable time to high level
S1 is closed, See Figure 4
tPZL Output enable time to low level
S1 is closed, See Figure 4
tPHZ Output disable time from high level
S1 is closed, See Figure 4
tPLZ Output disable time from low level
S1 is closed, See Figure 4
Power dissipation capacitance (each driver) Cpd (see Note 5)
S1 is open, See Figure 2
�?All typical values are at VCC = 5 V and TA = 25C.
NOTE 5: Cpd is used to estimate the switching losses according to PD = Cpd �?VCC2 �?f, where f is the switching frequency.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AM26C31Q AM26C31M
MIN TYP�?MAX
VOH High-level output voltage
IO = �?0 mA
2.2 3.4
VOL Low-level output voltage
IO = 20 mA
0.2 0.4
|VOD| Differential output voltage magnitude
RL = 100 Ω�?See Figure 1
∆|VOD| Change in magnitude of differential output voltage�?RL = 100 Ω�?See Figure 1
VOC Common-mode output voltage
RL = 100 Ω�?See Figure 1
∆|VOC| Change in magnitude of common-mode output voltage�?RL = 100 Ω�?See Figure 1
II Input current
VI = VCC or GND
IO(off) Driver output current with power off
VCC = 0
VO = 6 V
VO = �?.25 V
IOS Driver output short-circuit current
VO = 0
IOZ High-impedance off-state output current
VO = 2.5 V
VO = 0.5 V
ICC Quiescent supply current
IO = 0
VI = 0 V or 5 V
VI = 2.4 V or 0.5 V, See Note 4
Ci Input capacitance
�?All typical values are at VCC = 5 V and TA = 25C.
�?|VOD| and |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
NOTE 4: This parameter is measured per input. All other inputs are at 0 V or 5 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AM26C31Q AM26C31M
MIN TYP�?MAX
tPLH Propagation delay time, low- to high-level output
S1 is open, See Figure 2
tPHL Propagation delay time, high- to low-level output
S1 is open, See Figure 2
6.5 12
tsk(p) Pulse skew time (|tPLH �?tPHL|)
S1 is open, See Figure 2
tr(OD), tf(OD) Differential output rise and fall times
S1 is open, See Figure 3
tPZH Output enable time to high level
S1 is closed, See Figure 4
tPZL Output enable time to low level
S1 is closed, See Figure 4
tPHZ Output disable time from high level
S1 is closed, See Figure 4
tPLZ Output disable time from low level
S1 is closed, See Figure 4
Power dissipation capacitance (each driver) Cpd (see Note 5)
S1 is open, See Figure 2
�?All typical values are at VCC = 5 V and TA = 25C.
NOTE 5: Cpd is used to estimate the switching losses according to PD = Cpd �?VCC2 �?f, where f is the switching frequency.
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common-Mode Output Voltages
C2 = 40 pF
C3 = 40 pF
See Note A
TEST CIRCUIT
Input A (see Note B)
tPLH tPHL
Output Y
tsk(p)
Output Z
tPHL tPLH
NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR �?1 MHz, duty cycle �?50%, and tr, tf �?6 ns.
Figure 2. Propagation Delay Time and Skew Waveforms and Test Circuit
PARAMETER MEASUREMENT INFORMATION
C2 = 40 pF
C3 = 40 pF
See Note A
TEST CIRCUIT
Input A 3 V (see Note B)
Differential
10% 10%
tr(OD) tf(OD) VOLTAGE WAVEFORMS
NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR �?1 MHz, duty cycle �?50%, and tr, tf �?6 ns.
Figure 3. Differential-Output Rise- and Fall-Time Waveforms and Test Circuit
PARAMETER MEASUREMENT INFORMATION
Enable Inputs G
Input A
Output
(see Note B) G
See Note A
TEST CIRCUIT
Enable G Input
(see Note C)
Enable G Input
1.3 V 1.3 V
Output WIth
0 V to A Input VOL + 0.3 V
tPLZ Output WIth
1.5 V VOL
3 V to A Input
VOH �?0.3 V
tPHZ tPZH
VOLTAGE WAVEFORMS
NOTES: A. C1, C2, and C3 includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR �?1 MHz, duty cycle �?50%, tr < 6 ns, and tf < 6 ns.
C. Each enable is tested separately.
Figure 4. Output Enable- and Disable-Time Waveforms and Test Circuit
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SWITCHING FREQUENCY
VCC = 5 V TA = 25C See Figure 2
S1 Open
All Four Channels Switching Simultaneously
N Package
0 5 10 15 20 25
30 35 40
f �?Switching Frequency �?MHz
Figure 5
PACKAGE OPTION ADDENDUM 11-Feb-2005
PACKAGING INFORMATION
Orderable Device Status (1) Package
Package
Drawing
Pins Package
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-9163901Q2A ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC
5962-9163901QEA ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC
5962-9163901QFA ACTIVE CFP W 16 1 None A42 SNPB Level-NC-NC-NC
AM26C31CD ACTIVE SOIC D 16 40 Pb-Free
CU NIPDAU Level-2-250C-1 YEAR
AM26C31CDBLE OBSOLETE SSOP DB 16 None Call TI Call TI
AM26C31CDBR ACTIVE SSOP DB 16 2000 Pb-Free
AM26C31CDR ACTIVE SOIC D 16 2500 Pb-Free
AM26C31CN ACTIVE PDIP N 16 25 Pb-Free
AM26C31CNSR ACTIVE SO NS 16 2000 Pb-Free
AM26C31ID ACTIVE SOIC D 16 40 Pb-Free
CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR
AM26C31IDBLE OBSOLETE SSOP DB 16 None Call TI Call TI
AM26C31IDBR ACTIVE SSOP DB 16 2000 Pb-Free
AM26C31IDR ACTIVE SOIC D 16 2500 Pb-Free
AM26C31IN ACTIVE PDIP N 16 25 Pb-Free
AM26C31INSR ACTIVE SO NS 16 2000 Pb-Free
AM26C31IPW ACTIVE TSSOP PW 16 90 Pb-Free
CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
AM26C31MFKB ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC AM26C31MJB ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC AM26C31MWB ACTIVE CFP W 16 1 None A42 SNPB Level-NC-NC-NC AM26C31QD ACTIVE SOIC D 16 40 None CU NIPDAU Level-1-220C-UNLIM AM26C31QDR ACTIVE SOIC D 16 2500 None CU NIPDAU Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check for the latest availability information and additional product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
Addendum-Page 1
PACKAGE OPTION ADDENDUM 11-Feb-2005
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
16 15 14
26 27 28 1 2 3 4
0.020 (0,51)
0.010 (0,25)
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
0.045 (1,14)
0.035 (0,89)
4040140 / D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.
E. Falls within JEDEC MS-004
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,15 M
Gage Plane
Seating Plane
2,00 MAX
0,05 MIN
PINS ** DIM
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C �?JANUARY 1995 �?REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,10 M
0,15 NOM
Gage Plane
1,20 MAX
Seating Plane
PINS ** DIM
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 �?DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
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Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright �?2005, Texas Instruments Incorporated

product details:http://www.utsource.net/AS339M.html
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LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
General Description
The AS339/339A consist of four independent preci- sion voltage comparators with a typical offset voltage of 2.0mV and high gain. They are specifically designed to operate from a single power supply over wide range of voltages. Operation from split power supply is also possible and the low power supply cur- rent drain is independent of the magnitude of the power supply voltage.
The AS339/339A series are compatible with industry standard 339. AS339A has more stringent input offset voltage than AS339.
The AS339 is available in DIP-14, SOIC-14 and TSSOP-14 packages, AS339A is available in DIP-14 and SOIC-14 packages
Features
· Wide Supply Voltage Range
- Single Supply: 2.0V to 36V
- Dual Supplies: ±1.0V to ±18V
· Low Supply Current Drain: 0.9mA
· Low Input Bias Current: 25nA (Typical)
· Low Input Offset Current: ±5.0nA (Typical)
· Low Input Offset Voltage: 2.0mV (Typical)
· Input Common Mode Voltage Range Includes
· Differential Input Voltage Range Equals to the
Power Supply Voltage
· Low Output Saturation Voltage: 200mV at 4mA
· Open Collector Output
Applications
· Battery Charger
· Cordless Telephone
· Switching Power Supply
· DC-DC Module
· PC Motherboard
· Communication Equipment
DIP-14 SOIC-14 TSSOP-14
Figure 1. Package Types of AS339/339A
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Pin Configuration
M/P/G Package
SOIC-14/DIP-14/TSSOP-14
OUTPUT 2
OUTPUT 3
OUTPUT 1
OUTPUT 4
INPUT 1-
INPUT 4+
INPUT 1+
INPUT 4-
INPUT 2-
INPUT 3+
INPUT 2+
INPUT 3-
Figure 2. Pin Configuration of AS339/339A (Top View )
Functional Block Diagram
Q2 Q3
OUTPUT Q8
Figure 3. Functional Block Diagram of AS339/339A (Each comparator)
Ordering Information
Circuit Type
Blank: AS339
A: AS339A
AS339 -
E1: Lead Free Blank: Tin Lead TR: Tape and Reel
Blank: Tube
Package
M: SOIC-14
P: DIP-14
G: TSSOP-14
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Ordering Information (Continued)
Package
Temperature
Part Number
Marking ID
Packing Type
Tin Lead
Lead Free
Tin Lead
Lead Free
SOIC-14
-40 to 85oC
AS339M
AS339M-E1
AS339M
AS339M-E1
AS339MTR
AS339MTR-E1
AS339M
AS339M-E1
Tape & Reel
AS339AM-E1
AS339AM-E1
AS339AMTR-E1
AS339AM-E1
Tape & Reel
AS339P
AS339P-E1
AS339P
AS339P-E1
AS339AP-E1
AS339AP-E1
TSSOP-14
AS339G-E1
EGS339
AS339GTR-E1
EGS339
Tape & Reel
BCD Semiconductor's Pb-free products, as designated with "E1" suffix in the part number, are RoHS compliant.
Absolute Maximum Ratings (Note 1)
Parameter
Symbol
Supply Voltage
Differential Input Voltage
Input Voltage
-0.3 to 40
Input Current (VIN<-0.3V) (Note 2)
Output Short-Circuit to Ground
Continuous
Power Dissipation (TA=25oC)
DIP-14
SOIC-14
TSSOP-14
Operating Junction Temperature
Storage Temperature Range
-65 to 150
Lead Temperature (Soldering, 10 Seconds)
Note 1: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to "Absolute Maximum Ratings" for extended periods may affect device reliability.
Note 2: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than -0.3 VDC (at 25oC).
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Recommended Operating Conditions
Parameter
Symbol
Supply Voltage
Operating Temperature Range
Electrical Characteristics
Limits in standard typeface are for TA=25oC, bold typeface applies over TA=-40oC to 85oC (Note 3), VCC=5V, GND=0V, unless otherwise specified.
Note 3: Limits over the full temperature are guaranteed by design, but not tested in production.
Note 4: The input common-mode voltage of either input signal voltage should not be allowed to go negatively by more than 0.3V (at 25oC). The upper end of the common-mode voltage range is VCC-1.5V (at 25oC), but either or both inputs can go to +18V without damages, independent of the magnitude of the VCC.
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Typical Performance Characteristics
0 4 8 12 16 20 24 28 32 36
Supply Voltage (V)
0 4 8 12 16 20 24 28 32 36
Supply Voltage (V)
Figure 4. Supply Voltage vs. Supply Current Figure 5. Supply Voltage vs. Input Bias Current
0.01 0.1 1 10 100
Output Sink Current (mA)
0 0.2 0.4
0.6 0.8
1.0 1.2
Time (µs)
1.4 1.6
1.8 2.0
Figure 6. Output Sink Current vs. Saturation Voltage
Figure 7. Response Time for 5mV Input Overdrive - Negative Transition
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Typical Performance Characteristics (Continued)
0 0.2 0.4
0.6 0.8
1.0 1.2
1.4 1.6
1.8 2.0
Time (µs)
Figure 8. Response Time for 5mV Input Overdrive - Positive Transition
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Typical Applications
+VIN +
+VIN + 3
1/4 AS339/A VO
1/4 AS339/A O
Figure 9. Basic Comparator
Figure 10. Driving CMOS
1/4 AS339/A
1/4 AS339/A
0.001µF
1M 100K
Figure 11. One Shot Multivibrator Figure 12. Squarewave Oscillator
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Mechanical Dimensions
Unit: mm(inch)
1.524(0.060) TYP
1.600(0.063)
1.800(0.071)
0.700(0.028)
7.620(0.300)TYP
0.254(0.010)
0.360(0.014)
0.560(0.022)
0.510(0.020)MIN
2.540(0.100)TYP
3.000(0.118)
3.600(0.142)
0.130(0.005)MIN
0.204(0.008)
0.360(0.014)
8.200(0.323)
9.400(0.370)
1.600(0.063)
1.800(0.071)
Φ3.000(0.118) Depth
0.100(0.004)
0.200(0.008)
6.200(0.244)
6.600(0.260)
R1.000(0.039)
18.800(0.740)
19.200(0.756)
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Mechanical Dimensions (Continued)
SOIC-14
Unit: mm(inch)
0.700(0.028)
0.100(0.004)
0.250(0.010)
A 0.280(0.011) ×45°
0.480(0.019)×45°
8.550(0.337)
8.750(0.344)
3.800(0.150)
4.000(0.157)
0.330(0.013)
0.510(0.020)
1.270(0.050)
0.250(0.010)
0.200(0.008)MIN
R0.200(0.008)
R0.200(0.008)
φ2.000(0.079) Depth 0.060(0.002)
0.100(0.004)
0.500(0.020)
0.600(0.024)
0.250(0.010)
LOW POWER LOW OFFSET VOLTAGE QUAD COMPARATORS AS339/339A
Mechanical Dimensions (Continued)
TSSOP-14
Unit: mm(inch)
0.340(0.013)
0.540(0.021)
0.050(0.002)
0.150(0.006)
SEE DETAIL A
0.900(0.035)
1.050(0.041)
1.200(0.047) MAX
4.860(0.191)
5.060(0.199)
0.100(0.004)
0.190(0.007)
TOP&BOTTOM
R0.090(0.004)
0.200(0.008)
6.200(0.244)
6.600(0.260)
# 1 PIN
0.650(0.026)
φ 0.950(0.037)
1.050(0.041)
0.100(0.004)
4.300(0.169)
4.500(0.177)
0.200(0.008)
0.280(0.011)
0.250(0.010)
1.000(0.039) REF DETAIL A
R0.090(0.004)
0.450(0.018)
0.750(0.030)

IMPORTANT NOTICE
BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifi- cations herein. BCD Semiconductor Manufacturing Limited does not assume any responsibility for use of any its products for any particular purpose, nor does BCD Semiconductor Manufacturing Limited assume any liability arising out of the application or use of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or other rights nor the rights of others.
MAIN SITE
BCD Semiconductor Manufacturing Limited
- Wafer Fab
Shanghai SIM-BCD Semiconductor Manufacturing Limited
800, Yi Shan Road, Shanghai 200233, China
Tel: +86-21-6485 1491, Fax: +86-21-5450 0008
BCD Semiconductor Manufacturing Limited
- IC Design Group
Advanced Analog Circuits (Shanghai) Corporation
8F, Zone B, 900, Yi Shan Road, Shanghai 200233, China
Tel: +86-21-6495 9539, Fax: +86-21-6485 9673
REGIONAL SALES OFFICE
Shenzhen Office
Shanghai SIM-BCD Semiconductor Manufacturing Co., Ltd. Shenzhen Office
Advanced Analog Circuits (Shanghai) Corporation Shenzhen Office
27B, Tower C, 2070, Middle Shen Nan Road, Shenzhen 518031, China
Tel: +86-755-8368 3987, Fax: +86-755-8368 3166
Taiwan Office
BCD Semiconductor (Taiwan) Company Limited
4F, 298-1, Rui Guang Road, Nei-Hu District, Taipei, Taiwan
Tel: +886-2-2656 2808, Fax: +886-2-2656 2806
USA Office
BCD Semiconductor Corporation
3170 De La Cruz Blvd., Suite 105, Santa Clara, CA 95054-2411, U.S.A
Tel: +1-408-988 6388, Fax: +1-408-988 6386

If you want to buy this product please visit:http://www.datasheet-photos.com/Product/2N6660.html
Popular search:
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Ordering Information
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RDS(ON)
Order Number / Package
2N6660
2N6661
High Reliability Devices
See pages 5-4 and 5-5 for MILITARY STANDARD Process
Flows and Ordering Information.
Features
Free from secondary breakdown Low power drive requirement Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode
High input impedance and high gain
Complementary N- and P-channel devices
Applications Motor controls Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)
Absolute Maximum Ratings
Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage 20V Operating and Storage Temperature -55 C to +150 C Soldering Temperature* 300 C
* Distance of 1.6 mm from case for 10 seconds.
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Package Options
Case: DRAIN
Note: See Package Outline section for dimensions.
Thermal Characteristics
2N6660/2N6661
Package
ID (continuous)*
ID (pulsed)
Power Dissipation
@ TC = 25 C
2N6660
2N6661
* ID (continuous) is limited by max rated Tj.
Electrical Characteristics (@ 25 C unless otherwise specified)
Parameter
Conditions
Drain-to-Source
Breakdown Voltage
2N6660
VGS = 0V, ID = 10 A
2N6661
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID =1mA
VGS(th)
Change in VGS(th) with Temperature
VGS = VDS, ID =1mA
Gate Body Leakage
VGS = 20V, VDS = 0V
Zero Gate Voltage Drain Current
VGS = 0V, VDS = Max Rating
VGS = 0V, VDS = 0.8 Max Rating, TA = 125 C
ID(ON)
ON-State Drain Current
VGS = 10V, VDS = 10V
RDS(ON)
Static Drain-to-Source
ON-State Resistance
VGS= 5V, ID = 0.3A
2N6660
VGS = 10V, ID = 1A
2N6661
VGS = 10V, ID = 1A
Forward Transconductance
VDS = 25V, ID = 0.5A
Input Capacitance
VGS = 0V, VDS = 24V
f = 1 MHz
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Time
VDD = 25V,
ID = 1A, RGEN = 25
t(OFF)
Turn-OFF Time
Diode Forward Voltage Drop
VGS = 0V, ISD = 1A
Reverse Recovery Time
VGS = 0V, ISD = 1A
Notes:
1: All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300 s pulse, 2% duty cycle.)
2: All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
td(ON) tr
td(OFF) tF
PULSE GENERATOR
0V 90% 90%

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Popular search:
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N-Channel Enhancement-Mode
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Ordering Information
BVDSS / BVDGS
RDS(ON)
Order Number / Package
2N6660
2N6661
High Reliability Devices
See pages 5-4 and 5-5 for MILITARY STANDARD Process
Flows and Ordering Information.
Features
Free from secondary breakdown Low power drive requirement Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode
High input impedance and high gain
Complementary N- and P-channel devices
Applications Motor controls Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)
Absolute Maximum Ratings
Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage 20V Operating and Storage Temperature -55 C to +150 C Soldering Temperature* 300 C
* Distance of 1.6 mm from case for 10 seconds.
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Package Options
Case: DRAIN
Note: See Package Outline section for dimensions.
Thermal Characteristics
2N6660/2N6661
Package
ID (continuous)*
ID (pulsed)
Power Dissipation
@ TC = 25 C
2N6660
2N6661
* ID (continuous) is limited by max rated Tj.
Electrical Characteristics (@ 25 C unless otherwise specified)
Parameter
Conditions
Drain-to-Source
Breakdown Voltage
2N6660
VGS = 0V, ID = 10 A
2N6661
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID =1mA
VGS(th)
Change in VGS(th) with Temperature
VGS = VDS, ID =1mA
Gate Body Leakage
VGS = 20V, VDS = 0V
Zero Gate Voltage Drain Current
VGS = 0V, VDS = Max Rating
VGS = 0V, VDS = 0.8 Max Rating, TA = 125 C
ID(ON)
ON-State Drain Current
VGS = 10V, VDS = 10V
RDS(ON)
Static Drain-to-Source
ON-State Resistance
VGS= 5V, ID = 0.3A
2N6660
VGS = 10V, ID = 1A
2N6661
VGS = 10V, ID = 1A
Forward Transconductance
VDS = 25V, ID = 0.5A
Input Capacitance
VGS = 0V, VDS = 24V
f = 1 MHz
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Time
VDD = 25V,
ID = 1A, RGEN = 25
t(OFF)
Turn-OFF Time
Diode Forward Voltage Drop
VGS = 0V, ISD = 1A
Reverse Recovery Time
VGS = 0V, ISD = 1A
Notes:
1: All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300 s pulse, 2% duty cycle.)
2: All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
td(ON) tr
td(OFF) tF
PULSE GENERATOR
0V 90% 90%

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CS5505/6/7/8
Very Low Power, 16-bit & 20-bit A/D Converters
Features
l Very Low Power Consumption
- Single supply +5 V operation: 1.7 mW
- Dual supply ±5 V operation: 3.2 mW
l Offers superior performance to VFCs and multi-slope integrating ADCs
l Differential Inputs
- Single Channel (CS5507/8) and Four-Channel
(CS5505/6) pseudo-differential versions
l Either 5 V or 3.3 V Digital Interface
l Linearity Error:
- ±0.0015% FS (16-bit CS5505/7)
- ±0.0007% FS (20-bit CS5506/8)
l Output update rates up to 100 Sps
l Flexible Serial Port
l Pin-Selectable Unipolar/Bipolar Ranges
Description
The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes.
The CS5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input channels. The CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word.The CS5505/6/7/8 sample upon command up to 100 Sps.
The on-chip digital filter offers superior line rejection at
50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
The CS5505/6/7/8 include on-chip self-calibration cir- cuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors.
The CS5505/6/7/8 serial port offers two general-purpose modes for the direct interface to shift registers or syn- chronous serial ports of industry-standard microcontrollers.
ORDERING INFORMATION
See page 30.
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FERROXCUBE
Material specification
Supersedes data of September 2004 2008 Sep 01
Material specification 8C12
8C12 SPECIFICATIONS
High permeability specialty NiZn ferrite only used in large toroids and machined products mainly for scientific particle accelerators operating at frequencies up to 2 MHz.
SYMBOL CONDITIONS VALUE UNIT
�?s �? ''s
i 25 C; �?0 kHz;
0.25 mT
B 25 C; 10 kHz;
1200 A/m
100 C; 10 kHz;
1200 A/m
900 �?0%
�?260 mT
�?DC; 25 C �?105 m
TC �?125 C
density �?5100 kg/m3
f (MHz) 102
Fig.1 Complex permeability as a function of frequency.
MBW456
MBW457
T ( oC)
50 100
H (A/m)
Fig.2 Initial permeability as a function of temperature.
Fig.3 Typical B-H loops.
Material specification 8C12
DATA SHEET STATUS DEFINITIONS
DATA SHEET STATUS
Preliminary specification
PRODUCT
STATUS DEFINITIONS
Development This data sheet contains preliminary data. Ferroxcube reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification Production This data sheet contains final specifications. Ferroxcube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
DISCLAIMER
Life support applications �?These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Ferroxcube customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Ferroxcube for any damages resulting from such application.
PRODUCT STATUS DEFINITIONS
STATUS INDICATION DEFINITION
These are products that have been made as development samples for the purposes of
Prototype
technical evaluation only. The data for these types is provisional and is subject to change.
Design-in These products are recommended for new designs.
Preferred These products are recommended for use in current designs and are available via our sales channels.
Support These products are not recommended for new designs and may not be available through all of our sales channels. Customers are advised to check for availability.

product details:http://www.utsource.net/IR1150ISTRPBF.html
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IR1150ISTRPBF data
Data Sheet No. PD60230 revAa
IR1150S(PbF)
IR1150IS(PbF)
PFC ONE CYCLE CONTROL PFC IC
Features
�? PFC with IR proprietary “One Cycle Control�?�? Continuous conduction mode (CCM) boost type PFC
�? No line voltage sense required
�? Programmable switching frequency (50kHz-200kHz)
�? Programmable output overvoltage protection
�? Brownout and output undervoltage protection
�? Cycle-by-cycle peak current limit
�? Soft start
�? User initiated micropower “Sleep Mode�?Description
�? Open loop protection
�? Maximum duty cycle limit of 98%
�? User programmable fixed frequency operation
�? Min. off time of 150-350ns over freq range
�? VCC under voltage lockout
�? Internally clamped 13V gate drive
�? Fast 1.5A peak gate drive
�? Micropower startup (<200 A)
�? Latch immunity and ESD protection
�? Parts also available Lead-Free
Package
The PFC IR1150 is a power factor correction (PFC) control IC designed to operate in continuous conduction mode (CCM) over a wide range input line voltages. The IR1150 is based on IR's proprietary "One Cycle Control" (OCC) technique providing a cost effective solution for PFC. The proprietary control method allows major reductions in component count, PCB area and design time while delivering the same high system performance as traditional solutions.
The IC is fully protected and eliminates the often noise sensitive line voltage sensing requirements of existing solutions.
The IR1150 features include programmable switching frequency, programmable dedicated over voltage protection, soft start, cycle-by-cycle peak current limit, brownout, open loop, UVLO and micropower startup current.
8-Lead SOIC
In addition, for low standby power requirements (Energy Star, 1W Standby, Blue Angel, etc.), the IC can be driven into sleep mode with total current consumption below 200µA, by pulling the OVP pin below 0.62V.
IR1150 Application Diagram
BR ID GE
AC LI N E
AC NEUTRAL
IR 11 50
 +
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are absolute voltages referenced to COM. Thermal resistance and power dissipation are measured under board mounted and still air conditions.
Parameters
Symbols
Remarks
VCC voltage
Not internally clamped
Freq. voltage
VFREQ.
ISNS voltage
VFB voltage
COMP voltage
Gate voltage
Continuous gate current
Max peak gate current
IGATEPK
Junction temperature
Storage temperature
Thermal resistance
SOIC-8
Package power dissipation
SOIC-8 TAMB = 25oC
ESD protection
Human body model*
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameters
Symbols
Remarks
Supply voltage
Junction temperature
Ambient temperature
IR1150S
Ambient temperature
IR1150IS
Switching frequency
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from �?25 ° C to 125°C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition
Supply Section
Parameters
Symbols
Remarks
VCC turn-on threshold
VCC ON
VCC turn-off threshold
(under voltage lock out)
VCC UVLO
VCC turn-off hysteresis
VCC HYST
*Per EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5K�?series resistor)
Electrical Characteristics cont.
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from �?25° C to 125°C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Parameters
Symbols
Remarks
Operating current
CLOAD=1nF fSW=200kHZ
CLOAD=10nF fSW=200kHZ
Standby mode - inactive gate
Internal oscillator running
Startup current
ICCSTART
VCC=VCC ON -0.1V
Sleep current
ISLEEP
VOVP<0.5V (typ),VCC =15V
Sleep mode threshold
VSLEEP
VCC =15V
Oscillator Section
Parameters
Symbols
Remarks
Switching frequency
RSET = 165k�?-37k�?approx.
Initial accuracy
fSW ACC
TA = 25oC
Voltage stability
13V <VCC <20V
Temperature stability
-25oC ≤TJ�?25oC
Total variation
Line & temperature
Long term stability
FSTABLT
TAMB = 125oC, 1000Hrs
Maximum duty cycle
fSW=200kHz
Minimum duty cycle
Minimum off time
Toffmin
fSW=50kHz to 200kHz
Protection Section
Parameters
Symbols
Remarks
Open loop protection (OLP)
Vfb threshold
Output under voltage
protection (OUV)
Brown out protection
Output over voltage
protection (OVP)
OVP hysteresis
Peak current limit protection
(IPKLMT) ISNS voltage threshold
Internal Voltage Reference Section
Parameters
Symbols
Remarks
Reference voltage
TA = 25oC
Line regulation
13.5V <VCC < 20V
Temp stability
-25oC ≤TAMB�?25oC
Total variation
Over VCC and Tj ranges
Voltage Error Amplifier Section
Parameters
Symbols
Remarks
Transconductance
-25oC ≤TAMB�?25oC
Source/sink current
TAMB = 25oC
-25oC ≤TAMB�?25oC
Soft start delay time
(calculated)
RGAIN=1k�? CZERO=0.33F CPOLE=0.01F, fXO=28Hz
VCOMP voltage (fault)
VCOMP FLT
@ 1mA (max) initial
@ 25A steady state
Effective VCOMP voltage
VCOMP EFF
Input bias current
VFB=0V, -25oC ≤TAMB�?25oC
Open loop bandwidth
Input offset voltage temp coefficient
Common mode rejection ratio
Output low voltage
Output high voltage
VCOMP start voltage
VCOMP START
Current Amplifier Section
Parameters
Symbols
Remarks
DC gain
Corner frequency
Input offset voltage
ISNS bias current
VFB=0V,-25oC ≤TAMB�?25oC
Input offset voltage temp
coefficient
Common mode rejection ratio
Blanking time
TBLANK
TAMB = 25oC
-25oC ≤TAMB�?25oC
Gate Driver Section
Parameters
Symbols
Remarks
Gate low voltage
IGATE=200mA
Gate high voltage
VCC=20V
Gate high voltage
VCC =11.5V
Rise time
CLOAD = 1nF, VCC=16V
CLOAD = 10nF, VCC=16V
Fall time
CLOAD = 1nF, VCC=16V
CLOAD = 10nF, VCC=16V
Out peak current
CLOAD = 10nF, VCC=16V
Gate voltage @ fault
VG fault
IGATE=20mA
Block Diagram
BIAS & REFERENCES
OVP/EN 4
1.055VREF
2 FREQ
I SNS 3
DUTY CYCLE LIMIT
8 GATE
VFB 6 R Q
COMP 5
1 COM
FAULT PROTECTION
OPEN LOOP PROTECTION OUTPUT UNDER VOLTAGE
Lead Assignments & Definitions
Lead Assignment
Description
IR1150S
COM 1 8 GATE
FREQ 2 7 V CC
I SNS 3 6 VFB
OVP/EN 4 5 COMP
8 LEAD SOIC
Ground
Frequency Set
Current Sense
OVP/EN
Overvoltage Fault Detect / Enable
Voltage Loop Compensation
Output Voltage Sense
IC Supply Voltage
Gate Drive Output
General Description
The PFC IR1150 is intended for boost converters for power factor correction operating at a fixed
IC Supply
The UVLO circuit monitors the V
pin and maintains
frequency in continuous conduction mode. The IC
the gate drive signal inactive
until the V
pin voltage
operates with two loops; an inner current loop and
reaches the UVLO turn on threshold, (V
). As soon
an outer voltage loop. The inner current loop is fast,
as the V
voltage exceeds this
threshold, provided
reliable and does not require sensing of the input
that the VFB
pin voltage is greater than 20%V
voltage in order to create a current reference.
This inner current loop sustains the sinusoidal profile
gate drive will begin switching (under Soft Start) and increase the pulse width to its maximum value as demanded by the output voltage error amplifier. If
of the average input current based on the dependency
of the pulse width modulator duty cycle on the input
the voltage on the VCC
off threshold, (V
pin falls below the UVLO turn the IC turns off, gate drive is
line voltage in order to determine the analogous input
CC UVLO),
terminated, and the turn
on threshold must again be
line current. Thus, the current loop uses the
embedded input voltage signal to control the average input current to follow the input voltage.
The IR1150 enables excellent THD performance. In light load conditions, a small distortion occurs at zero- crossing due to the finite boost inductance but this is negligible and well within EN61000-3-2 Class D specifications.
The outer voltage loop controls the DC bus voltage. This voltage is fed into the voltage error amplifier to control the slope of the integrator ramp and sets the amplitude of the average input current.
The two loops combine to control the amplitude, phase and shape of the input current, with respect to the input voltage, giving near-unity power factor.
The IC is designed for robust operation and pro- vides protection from system level over current, over voltage, under voltage, and brownout conditions.
exceeded in order to re-start the process and move into Soft Start mode.
Soft Start
Soft Start controls the rate of rise of the output voltage error amplifier in order to obtain a linear control of the increasing duty cycle as a function of time. The Soft Start time is controlled by voltage error amplifier compensation components selected, and is user programmable based on desired loop crossover frequency.
Frequency Select
The switching frequency of the IC is programmable by an external resistor at the FREQ pin. The design incorporates min/max restrictions such that the minimum and maximum operating frequency fall within the range of 50-200kHz.
Gate Drive
The gate drive is a totem pole driver with 1.5A capability. If higher currents are required, additional external drivers can be used.
Detailed Pin Description
COM: Ground
This is the ground potential pin of the integrated con- trol circuit. All internal devices are referenced to this point.
VFB: Output Voltage Feedback
The output voltage of the boost converter is sensed
via a resistive divider and fed into this pin, which is the inverting input of the output voltage error amplifier. The impedance of the divider string must be low enough so as to not introduce substantial error due to the input bias currents of the amplifier, yet high enough so as to minimize power dissipation. A typical value of external divider impedance is 1M�?
The error amplifier is a transconductance type which yields high output impedance, thus increasing the noise immunity of the error amplifier output. This also eliminates input divider string interaction with compensation feedback capacitors and reducing the loading of divider string due to a low impedance output of the amplifier.
COMP: Voltage Loop Compensation
External circuitry from this pin to ground compensates the system voltage loop and soft start time. This is the output of the voltage error amplifier. This pin will be discharged via internal resistance when a fault mode occurs.
GATE: Gate Drive Output
This is the gate drive output of the IC. Drive voltage is internally limited and provides ±1.5A peak with matched rise and fall times.
FREQ: Frequency Set
This is the user programmable frequency pin. An external resistor from this pin to the COM pin pro- grams the frequency. The operational switching fre- quency range for the device is 50kHz �?200kHz.
ISNS: Current Sense input
This pin is the inverting Current Sense Input & Peak
Current Limit. The voltage at this pin is the negative voltage drop, sensed across the system current sense resistor, representing the inductor current. This voltage is fed into the Peak Current Limit pro- tection comparator with threshold arond -1V. This pro- tection circuit incorporates a leading edge blanking circuit following the comparator to improve noise immunity of the protection process.
The current sense signal is also fed into the current sense amplifier. The signal is amplified, filtered of high frequency noise and then injected into a sum- ming node where it is subtracted from the compen- sation voltage VCOMP.
The signal on this pin must be previously filtered
with an RC cell to provide additional noise immunity. The input impedance of this pin is 5k�?
VCC: Supply Voltage
This is the supply voltage pin of the IC and it is
monitored by the under voltage lockout circuit. It is possible to turn off the IC by pulling this pin below the minimum turn off threshold voltage, without damage to the IC.
To prevent noise problems, a bypass ceramic capacitor connected to VCC and COM should be placed as close as possible to the IR1150S.
This pin is not internally clamped, therefore damage will occur if the maximum voltage is exceeded.
OVP/EN: Over Voltage Protection / Enable This pin is the input to the over voltage protection comparator the threshold of which is internally pro- grammed to 105.5% of V .
A resistive divider feeds this pin from the output volt- age to COM and inhibits the gate drive whenever the threshold is exceeded. Normal operation resumes when the voltage level on this pin decreases to be- low the pin threshold.
This pin is also used to activate “sleep�?mode by pulling the voltage level below 0.62V (typ).
Operating States
UVLO Mode
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold voltage, VCC ON.
During the time the IC remains in the UVLO state, the gate drive circuit is inactive and the IC draws a quiescent current of ICC START. The UVLO mode is accessible from any other state of operation whenever the IC supply voltage condition of VCC < VCC UVLO occurs.
Standby Mode
The IC is in this state if the supply voltage has exceeded VCC ON and the VFB pin voltage is less than 20% of VREF . The oscillator is running and all internal circuitry is biased in this state but the gate is inactive. This state is accessible from any other state of operation except OVP. The IC enters this state whenever the VFB pin voltage has decreased to 50% of VREF when operating in normal mode or during a peak current limit fault condition, or 20% VREF when operating in soft start mode.
Soft Start Mode
This state is activated once the VCC voltage has exceeded VCCON and the VFB pin voltage has exceeded 20% of VREF.
The soft start time, which is defined as the time required for the duty cycle to linearly increase from zero to maximum, is dependent upon the values selected for compensation of the voltage loop pin COMP to pin COM. Throughout the soft start cycle, the output of the voltage error amplifier (pin COMP) charges through the compensation network. This forces a linear rise of the voltage at this node which in turn forces a linear increase in the gate drive duty cycle from 0. This controlled duty cycle reduces system component stress during start up conditions as the input current amplitude is increasing linearly.
Normal Mode
The IC enters normal operating mode once the soft start transition has been completed. At this point the gate drive is switching and the IC draws a maximum of ICC from the supply voltage source. The device will initiate another soft start sequence in the event of a shutdown due to a fault, which activates the protection circuitry, or if the supply voltage drops below the UVLO turn off threshold of VCC UVLO.
Fault Protection Mode
The fault mode will be activated when any of the protection circuits are activated. The IC protection circuits include Supply Voltage Under Voltage Lockout (UVLO), Output Over Voltage Protection (OVP), Open Loop Protection (OLP), Output Undervoltage Protection (OUV), and Peak Current Limit Protection (IPK LIMIT).
Sleep Mode
The sleep mode is initiated by pulling the OVP pin below 0.62V (typ). In this mode the IC draws a very low quiescent supply current.
STATE & TRANSITIONS DIAGRAM
AC POWER ON
Gate Inactive
Oscillator Inactive
UVLO VCC < VCCon Gate Inactive
Oscillator Inactive
I CC MAX = 200uA
VCC > VCCon
VOVP <0.7V Gate Inactive
Oscillator Inactive
I CC max = 200uA
VCC < VCC UVLO
STAND- BY VFB < 20%VREF Gate Inactive
Oscillator Active
I CC MAX = 4mA
VOVP >0.7 V VOVP <0.7V
VFB > 20% VREF
VFB < 50% VREF
VCC < VCC UVLO
I PK LIMIT
VCC < VCC UVLO
VFB < 20% VREF
SOFT START
VFB < 80% VREF
VISNS < -1.0V Present PulseTerminated
Oscillator Active
VISNS < -1.0V
VISNS > -1.0V
Gate Active
Oscillator Active
Pulse Width Increasing
0- 97 % Duty Cycle
VOVP <0.7V
VFB > 80% VREF
VCC < VCC UVLO
VISNS < -1.0V VISNS > -1.0V
Gate Active
Oscillator Active
I CC MAX = 28 mA
VFB < 50% VREF
VOVP <0.7 V
VOVP < 101% VREF
VOVP > 105% VREF
OVP FAULT VOVP > 105% VREF Gate Inactive
Oscillator Active
VOVP <0.7V
VCC < VCC UVLO
VOVP <0.7 V
10 12 V
1 11 V
VCC ON
VCC UVLO
5 V 10 V 15 V 20 V 25 V Supply voltage
-50 °C 0 °C 50 °C 100 °C 150 °C Temperature
Fig.1 - Supply Current Fig. 2 - Under Voltage Lockout vs.
Temperature
300 kHz
250 kHz
250 kHz
200 kHz
200 kHz
150 kHz
100 kHz
100 kHz
RF =165k
50 kHz
0 k 50 k 100 k 150 k 200 k
Programming Resistor
-50 °C 0 °C 50 °C 100 °C 150 °C Temperature
Fig. 3 - Oscillator Frequency vs.
Programming Resistor
Fig. 4 - Oscillator Frequency vs.
Temperature
-50 °C 0 °C 50 °C 100 °C 150 °C Temperature
-50 °C 0 °C 50 °C 100 °C 150 °C Temperature
Fig. 5 - Reference Voltage Fig. 6 - Voltage Error Amplifier
Transconductance
IO (source) IO (sink)
-50 °C 0 °C 50 °C 100 °C 150 °C Temperature
-50 °C 0 °C 50 °C 100 °C 150 °C Temperature
Fig.7 - Voltage Error Amplifier
Source/Sink Current
Fig. 8 - Current Sense Amplifier DC Gain
IR1150 Timing Diagrams
13.0V (typ)
11.0V (typ)
UVLO NORMAL UVLO
Vcc Under Voltage Lockout
82% VREF
 106% VREF
100% VREF
51% VREF
19% VREF
SOFT START
Output Protection
Case outline
D B DIM
IN C HES MIN MAX
MILLIMETERS MIN MAX
A 5 FOOTPR INT
8X 0.72 [.028]
A .0532
A1 .0040 b .013
8 7 6 5
c .0075 .0098 0.19 0.25
E 0.25 [.010] A
D .189
E .1497
1 2 3 4
6.46 [.255]
e .050 B ASIC
1.27 B ASIC
e 1 .025 B ASIC 0.635 B ASIC
6X e
3X 1.27 [.050] 8X 1.78 [.070]
H .2284
K .0099
L .016 y 0°
e1 K x 45° A
8X b A1
0.10 [.004]
8X L 8X c
0.25 [.010] C A B 7
NO TES:
1. DIMENS ION ING & TOLERANC ING PE R ASME Y14.5M-1994.
2. C O NTRO LLING DIMEN SIO N: MILLIMETER
3. DIMENS ION S AR E SHO WN IN MILLIME TE RS [INC HES].
4. O UTLIN E C O NF ORMS TO JEDEC OU TLINE MS-012AA.
5 DIMEN SIO N DO ES NO T IN C LUDE MO LD PR OTRUS ION S.
MO LD P RO TR USIO N S NO T TO E XC EED 0.15 [.006].
6 DIMEN SIO N DO ES NO T IN C LUDE MO LD PR OTRUS ION S.
MO LD P RO TR USIO N S NO T TO E XC EED 0.25 [.010].
7 DIMEN SIO N IS THE LE NG TH OF LEAD FO R SO LDE RING TO A SUBS TRATE.
01-6027
8-Lead SOIC
01-0021 11 (MS-012AA)
Tape & Reel Information
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
2. CONTROLLING DIMENSION : MILLIMETER.
FEED DIRECTION
330.00 (12.992) MAX.
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
14.40 ( .566 )
12.40 ( .488 )
PART MARKING INFORMATION
LOT CODE
ORDER INFORMATION
Basic Part
8-Lead SOIC IR1150STR order IR1150STR
8-Lead SOIC IR1150ISTR order IR1150ISTR
Lead-free Part
8-Lead SOIC IR1150S order IR1150STRPbF
8-Lead SOIC IR1150ISTR order IR1150ISTRPbF
The IR1150S(PbF) has been designed and qualified for the Consumer Market The IR1150IS(PbF) has been designed and qualified for the Industrial Market Qualification Standards can be found on IR’s Web site.
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/13/2005

Japan's successful start of the Korea Minion 2 per period across the Korean Peninsula

Korean dirt discovery spacecraft "Arirang" is 18 am local occasion in Japan's Tanegashima Latitude Establish Converge was successfully launched. In the tomorrow, "Arirang" twice a day through the Korean Peninsula, filming the Earth image.

The pertinent departments of Korea said in a report that "Arirang" has been undecided too panels, into the stable manoeuvring, complete the intelligence receiver and the acolyte excuse sediment station.

"Arirang" in the firing of rockets carrying four satellites in the at daybreak morning of the 18th, the opening separation, and then adjust the aspect to the sun, within five minutes in category to unregulated the three solar panels, and universal cycle in favour of battery supply , completed the preceding work.

Preparations, "Arirang" and Antarctic Norwegian trolls (Troll) core on the tack functioning of the sycophant within the first off import is received. After nearly the same hour, "Arirang", for the Korean Peninsula to complete the report receiving base station with the Korea Aerospace Probing Institute.

"Arirang" compel be 98 minutes a heyday to recur there the loam 14 laps, shooting Planet image. Shire time constantly 1:30 and 1:00, "Arirang" inclination be the speediness of 7.4 kilometers per later crossing past the Korean Peninsula. The aide carried through high-performance optical digital camera replica dauntlessness of 0.7 m bulldoze, not alone can distinguish between the launch of the procedure car-sized models, but also to catch sight of only of the people queuing.

"Arirang", the profitable get going of South Korea as the In agreement States, Europe and Israel to the four countries take to associate less than a man meter reality of commercial satellite.http://16e35.com/story.php?id=25667

The Korean rule plans to fling four satellites this year. In the bat of an eye half of this year, Korea want pitch in the rain can also knock off images of "Arirang" satellite. "Arirang" and "Arirang" can be the enumerate of observations on the Korean peninsula increased from 0.7 times a day to 3.5 times.

Japan's fundamental commercial launches of unknown satellites http://mfwilife.com/story.php?id=26813

Xinhua Dope Agency, Tokyo, May 18 (Commentator Lan Jianzhong) - The Japan Aerospace Reconnaissance Agency and Mitsubishi Heavy Industries Ltd. 18 am 39 pm (GMT 0 18 39 points), on Tanegashima Holm in Kagoshima Prefecture, the macrocosm center H2A climb launched three satellites, where a South Korean acolyte, which is Japan's in front commercial launches of non-native satellites.

"Arirang", the Korea Aerospace Inquire into Introduce developed a multi-purpose sputnik, equipped with optical cameras that can bound high-resolution photos in the service of mapping, environmental aegis and agriculture and other fields. In addition, also launched via Japan Aerospace investigating and development institutions hydrological cycle changes in utterance disciple droplets and Kyushu University, Desire Feng "pocket-sized satellites.

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Details have proved that this does support decrease the car to enter the ecological zones Shouguang, Shandong Province, identified because the "Hometown of Chinese veggies, Track Xiaojun right here for fifteen many years," the distributors " Zhang in entrance, must be billed, and launched the revenue is" environmental maintenance costs "who lives in Lu Village, the villagers to shun (voice) said," We're right here highway is quite narrow, and now a weekend on the obstruct, which heads a car, the other finish to a vehicle, it might not go high to shun stated Sam Creek was referred to as the Global Sluggish City, there's some truth

Accelerate the institution of the "three red lines" index program of h2o source managementXinhua Beijing, May well 8 (in tranquil) The reporter discovered in the nationwide h2o resources function conference around the eighth of the year, China will accelerate the decomposition of water resources development control, manage of drinking water use effectiveness, drinking water function location to restrict pollutant "three red lines" indicators to make sure that through the yr to establish protect river basin and provincial metropolitan areas and counties in 3 administrative areas of your red line indicator program Party along with the people firmly think that youthful persons of all ethnic teams in China is going to be terrific trust, satisfy our mission to make a far more breathtaking youth efficiency on the journey of creating a reasonably prosperous culture, to uphold and develop socialism with Chinese characteristics, to reach the wonderful rejuvenation in the Chinese nation! Author: Xiao Zhitao Huajie92 ministries and commissions within per week, the general public sector price range experts say not the far more detailed the better[Core] this calendar year will be the third yr on the central ministries to advertise the division budget manifeste Generally carried out about the water-saving irrigation location, business enterprise as well as other actions to make Consumer question: the federal government really should be responsible for this fear, as well as the "environmental protection" costs are affordable, customers are also extra concerned concerning the slow-City area of ​​ecological protection Who will spend for

Shu-Fen Wang, chief expert with the vegetable sector of contemporary agricultural industrial system in Shandong Province, stated that to stabilize vegetable output, but even better within the growth of such facilities and vegetables in Shandong location, with superior planting methods and pest manage technology, farmers within the proportion of only 30%59 billion, increased by 37 (Image) In current many years, with Nanjing the Gaochun Sam Town "slow city" popularity is steadily expanding, traveling by vehicle to feel the "slow Ray Ban life" to "slow city" the RayBan public is more and extra Zhang received environmental maintenance fee "should be the identical kind of charges

The geographical distribution on the rich wealth also synchronize dispersed, 5 to the wealthy, has a fortune of one Chongqing, Jiangsu, Shandong, Henan, Beijing, Shanghai and other provinces and metropolitan areas to attain complete protection of crucial h2o perform area drinking water good quality monitoring; start the countrys significant h2o source Ray Ban wayfarer of drinking water safety and Ray Ban safety requirements construction The environmental tour only towards the Peach Blossom Lover Plaza, he suggested need to be Finished Specifically the "last mile", sometimes the price tag of veggies will rise to double

"In reality, the villagers very simple wish instead of because of the scenic fees are met Together with the spending budget open to further advance from your Ray Ban wayfarer departments price range number "between the lines, can have an understanding of and study far more and more2 yuan 3, a feminine staff of your hospitals administrative office confirmed the cesspool stabbing incident, but the staff declined an interview, declined to disclose any particulars, stated the hospital will "properly handle"

To the vast quantity of young folks, Hu Jintao produced a five-point hope5% and five Zhang, 51 day, they spend the fee can nonetheless push into the scenic Zhang in the scenic location in the entrance in front of cars waiting around in a queue

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